View SPC564A74L7CFAY_8309900.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

september 2013 doc id 15399 rev 9 1/157 1 spc564a74b4, spc564a74l7, spc564a80b4, spc564a80l7 32-bit mcu family built on the embedded power architecture ? features 150 mhz e200z4 power architecture ? core ? variable length instruction encoding (vle) ? superscalar architecture with 2 execution units ? up to 2 integer or floating point instructions per cycle ? up to 4 multiply and accumulate operations per cycle memory organization ? 4 mb on-chip flash memory with ecc and read while write (rww) ? 192 kb on-chip ram with standby functionality (32 kb) and ecc ? 8 kb instruction cache (with line locking), configurable as 2- or 4-way ? 14 + 3 kb etpu code and data ram ?5 ? 4 crossbar switch (xbar) ? 24-entry mmu ? external bus interface (ebi) with slave and master port fail safe protection ? 16-entry memory protection unit (mpu) ? crc unit with 3 sub-modules ? junction temperature sensor interrupts ? configurable interrupt controller (with nmi) ? 64-channel dma serial channels ?3 ? esci ?3 ? dspi (2 of which support downstream micro second channel [msc]) ?3 ? flexcan with 64 messages each ?1 ? flexray module (v2.1) up to 10 mbit/s with dual or single channel and 128 message objects and ecc 1 ? emios 1 ? etpu2 (second generation etpu) 2 enhanced queued analog-to-digital converters (eqadcs) on-chip can/sci/flexray bootstrap loader with boot assist module (bam) nexus: class 3+ for co re; class 1 for the etpu jtag (5-pin) development trigger semaphore (dts) clock generation ? on-chip 4?40 mhz main oscillator ? on-chip fmpll (frequency-modulated phase-locked loop) up to 120 general purpose i/o lines power reduction mode: slow, stop and stand- by modes flexible supply scheme ? 5 v single supply with external ballast ? multiple external supply: 5 v, 3.3 v and 1.2 v designed for lqfp176, lbga208, pbga324 and known good die (kgd) lbga208 pbga324 lqfp176 table 1. device summary memory flash size part number package lqfp176 package: lbga208 package: pbga324 kgd 4mb spc564a80l7 - spc564a80b4 - 3mb spc564a74l7 - spc564a74b4 - www.st.com
contents spc564a74l7, spc564a80b4, spc564a80l7 2/157 doc id 15399 rev 9 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3 device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.4 spc564a80 feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.5 feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.5.1 e200z4 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.5.2 crossbar switch (xbar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.5.3 edma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.5.4 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.5.5 memory protection unit (mpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.5.6 fmpll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.5.7 siu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.5.8 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.5.9 bam . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.5.10 emios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.5.11 etpu2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.5.12 reaction module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.5.13 eqadc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.5.14 dspi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.5.15 esci . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.5.16 flexcan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.5.17 flexray . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.5.18 system timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.5.19 software watchdog timer (swt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.20 cyclic redundancy check (crc) module . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.21 error correction status module (ecsm) . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.22 external bus interface (ebi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.5.23 calibration ebi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.5.24 power management controller (pmc) . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.5.25 nexus port controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.5.26 jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.5.27 development trigger semaphore (dts) . . . . . . . . . . . . . . . . . . . . . . . . 29 1.6 spc564a80 series architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
spc564a74l7, spc564a80b4, spc564a80l7 contents doc id 15399 rev 9 3/157 1.6.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.6.2 block summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2 pinout and signal descrip tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.1 lqfp176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.2 lbga208 ballmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.3 pbga324 ballmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.4 signal summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.5 signal details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 3.1 parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 3.2 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 3.3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 3.3.1 general notes for specifications at maximum junction temperature . . . 85 3.4 emi (electromagnetic interference) characteristics . . . . . . . . . . . . . . . . . 88 3.5 electrostatic discharge (esd) characteristics . . . . . . . . . . . . . . . . . . . . . 88 3.6 power management control (pmc) and power on reset (por) electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 3.6.1 regulator example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 3.6.2 recommended power transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 3.7 power up/down sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 3.8 dc electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 3.9 i/o pad current specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 3.9.1 i/o pad v rc33 current specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 102 3.9.2 lvds pad specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 3.10 oscillator and pllmrfm electrical characteristics . . . . . . . . . . . . . . . . 104 3.11 temperature sensor electrical characterist ics . . . . . . . . . . . . . . . . . . . . 106 3.12 eqadc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 3.13 configuring sram wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 3.14 platform flash controller electrical charac teristics . . . . . . . . . . . . . . . . . 109 3.15 flash memory electrical char acteristics . . . . . . . . . . . . . . . . . . . . . . . . . 109 3.16 ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 3.16.1 pad ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 3.17 ac timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
contents spc564a74l7, spc564a80b4, spc564a80l7 4/157 doc id 15399 rev 9 3.17.1 reset and configuration pin timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 3.17.2 ieee 1149.1 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 3.17.3 nexus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 3.17.4 external bus interface (ebi) and calibration bus interface timing . . . . 122 3.17.5 external interrupt timing (irq pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 3.17.6 etpu timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 3.17.7 emios timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 3.17.8 dspi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 3.17.9 eqadc ssi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 3.17.10 flexcan system clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 4 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 4.1 ecopack ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 4.2 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 4.2.1 lqfp176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 4.2.2 bga208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 4.2.3 pbga324 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 5 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 6 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
spc564a74l7, spc564a80b4, spc564a80l7 list of tables doc id 15399 rev 9 5/157 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. spc564a80, spc563m64 and spc564a70 comparison . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3. spc564a80 series block summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 4. spc564a80 signal properties. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 5. pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 6. signal details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 7. power/ground segmentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 8. parameter classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 9. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 10. thermal characteristics for 176-pin qfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 11. thermal characteristics for 208-pin lbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 12. thermal characteristics for 324-pin pbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 13. emi testing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 14. esd ratings, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 15. pmc operating conditions and external regulators supply voltage . . . . . . . . . . . . . . . . 89 table 16. pmc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 17. spc564a80 external network specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 18. recommended operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 19. power sequence pin states (fast pads). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 table 20. power sequence pin states (medium, slow, and multi-voltage pads) . . . . . . . . . . . . . . . . . 94 table 21. dc electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 22. i/o pad average i dde specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 23. i/o pad v rc33 average i dde specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 24. v rc33 pad average dc current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 25. dspi lvds pad specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 26. pllmrfm electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 04 table 27. temperature sensor electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 28. eqadc conversion specifications (operating) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 29. eqadc single ended conversion specifications (operating). . . . . . . . . . . . . . . . . . . . . . . 107 table 30. eqadc differential ended conversion specifications (operating) . . . . . . . . . . . . . . . . . . . 107 table 31. cutoff frequency for additional sram wait state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 32. apc, rwsc, wwsc settings vs. frequency of operation , . . . . . . . . . . . . . . . . . . . . . . . . 109 table 33. flash program and erase specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 34. flash module life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 35. pad ac specifications (5.0 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 36. pad ac specifications (v dde = 3.3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 37. reset and configuration pin timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 table 38. jtag pin ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 15 table 39. nexus debug port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 40. nexus debug port operating frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 41. external bus interface maximum operating frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 42. calibration bus interface maximum operating frequency . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 43. external bus interface (ebi) and calibration bus operation timing . . . . . . . . . . . . . . . . . 122 table 44. external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 45. etpu timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 46. emios timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 table 47. dspi channel frequency support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 27 table 48. dspi timing , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
list of tables spc564a74l7, spc564a80b4, spc564a80l7 6/157 doc id 15399 rev 9 table 49. eqadc ssi timing characteristics (pads at 3.3 v or at 5.0 v) . . . . . . . . . . . . . . . . . . . . . 135 table 50. flexcan engine system clock divider threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 51. flexcan engine system clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 52. lqfp176 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 table 53. lbga208 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 table 54. pbga324 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 table 55. order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 table 56. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
spc564a74l7, spc564a80b4, spc564a80l7 list of figures doc id 15399 rev 9 7/157 list of figures figure 1. spc564a80 series block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 figure 2. 176-pin lqfp pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 3. 208-pin lbga package ballmap (viewed from above) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 4. 324-pin pbga package ballmap (northwest, viewed from above) . . . . . . . . . . . . . . . . . . . 37 figure 5. 324-pin pbga package ballmap (southwest, viewed from above) . . . . . . . . . . . . . . . . . . . 38 figure 6. 324-pin pbga package ballmap (northeast, viewed from above) . . . . . . . . . . . . . . . . . . . 39 figure 7. 324-pin pbga package ballmap (southeast, viewed from above) . . . . . . . . . . . . . . . . . . . 40 figure 8. core voltage regulator controller external components preferred configuration . . . . . . . . . 93 figure 9. pad output delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 figure 10. reset and configuration pin timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 14 figure 11. jtag test clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 12. jtag test access port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 13. jtag jcomp timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 figure 14. jtag boundary scan timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 figure 15. nexus output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 figure 16. nexus event trigger and test clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 figure 17. nexus tdi, tms, tdo timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 figure 18. clkout timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 figure 19. synchronous output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 figure 20. synchronous input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 figure 21. ale signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 figure 22. external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 figure 23. dspi classic spi timing ? master, cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 figure 24. dspi classic spi timing ? master, cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 figure 25. dspi classic spi timing ? slave, cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 figure 26. dspi classic spi timing ? slave, cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 figure 27. dspi modified transfer format timing ? master, cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . 132 figure 28. dspi modified transfer format timing ? master, cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . 132 figure 29. dspi modified transfer format timing ? slave, cpha =0. . . . . . . . . . . . . . . . . . . . . . . . . 133 figure 30. dspi modified transfer format timing ? slave, cpha =1. . . . . . . . . . . . . . . . . . . . . . . . . 134 figure 31. dspi pcs strobe (pcss) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 34 figure 32. eqadc ssi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 figure 33. lqfp176 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 figure 34. pbga324 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 figure 35. product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
introduction spc564a74l7, spc564a80b4, spc564a80l7 8/157 doc id 15399 rev 9 1 introduction 1.1 document overview this document provides electrical specific ations, pin assignments, and package diagrams for the spc564a80 series of microcontroller un its (mcus). for functional characteristics, refer to the spc564a80 microcontroller reference manual. 1.2 description the microcontroller?s e200z4 host processor core is built on power architecture technology and designed specifically for embedded applications. in addition to the power architecture technology, this core supports instructions for digital signal processing (dsp). the spc564a80 has two levels of memory hierarchy consisting of 8 kb of instruction cache, backed by 192 kb on-chip sram and 4 mb of internal flash memory. the spc564a80 includes an external bus interface, and also a calibration bus that is only accessible when using the calibration tools. this document describes the features of the spc564a80 and highlights important electrical and physical characteristics of the device.
spc564a74l7, spc564a80b4, spc564a80l7 introduction doc id 15399 rev 9 9/157 1.3 device comparison ta bl e 2 summarizes the spc564a80 and compares it to the spc563m64. table 2. spc564a80, spc563m64 and spc564a70 comparison feature spc564a80 spc563m64 spc564a70 process 90 nm core e200z4 e200z3 e200z4 simd yes vle yes cache 8 kb instruction no 8 kb instruction non-maskable interrupt (nmi ) nmi & critical interrupt mmu 24 entry 16 entry 24 entry mpu 16 entry no 16 entry crossbar switch 5 ? 43 ? 44 ? 4 core performance 0?150 mhz 0?80 mhz 0?150 mhz windowing software watchdog yes core nexus class 3+ class 2+ class 3+ sram 192 kb 94 kb 128 kb flash 4 mb 1.5 mb 2 mb flash fetch accelerator 4 ? 256-bit 4 ? 128-bit external bus 16-bit (incl 32-bit muxed) none calibration bus 16-bit (incl 32-bit muxed) 16-bit 16-bit (incl 32-bit muxed) dma 64 ch. 32 ch. 64 ch. dma nexus none serial 3 2 3 esci_a yes (msc uplink) esci_b yes (msc uplink) esci_c yes no yes can 3 2 3 can_a 64 buf can_b 64 buf no 64 buf can_c 64 buf 32 buf 64 buf spi 3 2 3
introduction spc564a74l7, spc564a80b4, spc564a80l7 10/157 doc id 15399 rev 9 micro second channel (msc) bus downlink ye s dspi_a no dspi_b yes (with lvds) dspi_c yes (with lvds) dspi_d yes no yes flexray yes no yes system timers 5 pit channels 4 stm channels 1 software watchdog emios 24 ch. 16 ch. 24 ch. etpu 32 ch. etpu2 code memory 14 kb data memory 3 kb interrupt controller 486 ch. (1) 307 ch. 486 ch. (1) adc 40 ch. 34 ch. 40 ch. adc_a yes adc_b yes temp sensor yes variable gain amp. yes decimation filter 2 1 2 sensor diagnostics yes crc yes no yes fmpll yes vrc yes supplies 5 v, 3.3 v (2) 5v, 3.3v (3) 5v, 3.3v (2) low-power modes stop mode slow mode packages lqfp176 (4) lbga208 (4) pbga known good die (kgd) 496-pin csp (5) lqfp100 lqfp144 lqfp176 lbga208 496-pin csp (5) lqfp176 (4) lbga208 (4) pbgaknown good die (kgd) 496-pin csp (5) 1. 199 interrupt vectors are reserved. 2. 5 v single supply only for lqfp176. 3. 5 v single supply only for lqfp144 and lqfp100. 4. pinout compatible with stmicroelectronics? spc563m64 devices. 5. for st calibration tool only. table 2. spc564a80, spc563m64 and spc564a70 comparison (continued) feature spc564a80 spc563m64 spc564a70
spc564a74l7, spc564a80b4, spc564a80l7 introduction doc id 15399 rev 9 11/157 1.4 spc564a80 feature list 150 mhz e200z4 power architecture core ? variable length instruction encoding (vle) ? superscalar architecture with 2 execution units ? up to 2 integer or floating point instructions per cycle ? up to 4 multiply and accumulate operations per cycle memory organization ? 4 mb on-chip flash memory with ecc and read while write (rww) ? 192 kb on-chip sram with standby functionality (32 kb) and ecc ? 8 kb instruction cache (with line lock ing), configurable as 2- or 4-way ? 14 + 3 kb etpu code and data ram ?5 ? 4 crossbar switch (xbar) ? 24-entry mmu ? external bus interface (ebi) with slave and master port fail safe protection ? 16-entry memory protection unit (mpu) ? crc unit with 3 sub-modules ? junction temperature sensor interrupts ? configurable interrupt controller (with nmi) ? 64-channel dma serial channels ?3 ? esci ?3 ? dspi (2 of which support downstream micro second channel [msc]) ?3 ? flexcan with 64 messages each ?1 ? flexray module (v2.1) up to 10 mbit/s with dual or single channel and 128 message objects and ecc 1 ? emios: 24 unified channels 1 ? etpu2 (second generation etpu) ? 32 standard channels ?1 ? reaction module (6 channels with three outputs per channel) 2 enhanced queued analog-to-digital converters (eqadcs) ? forty 12-bit input channels (multiplexed on 2 adcs); expandable to 56 channels with external multiplexers ? 6 command queues ? trigger and dma support ? 688 ns minimum conversion time on-chip can/sci/flexray bootstrap loader with boot assist module (bam) nexus ? class 3+ for the e200z4 core ? class 1 for the etpu jtag (5-pin)
introduction spc564a74l7, spc564a80b4, spc564a80l7 12/157 doc id 15399 rev 9 development trigger semaphore (dts) ? register of semaphores (32-bits) and an identification register ? used as part of a triggered data acquisition protocol ? evto pin is used to communicate to the external tool clock generation ? on-chip 4?40 mhz main oscillator ? on-chip fmpll (frequency-modulated phase-locked loop) up to 120 general purpose i/o lines ? individually programmable as input, output or special function ? programmable threshold (hysteresis) power reduction mode: slow, stop and stand-by modes flexible supply scheme ? 5 v single supply with external ballast ? multiple external supply: 5 v, 3.3 v and 1.2 v packages ?lqfp176 ? lbga208 ? pbga324 ? known good die (kgd) ? 496-pin csp (calibration tool only)
spc564a74l7, spc564a80b4, spc564a80l7 introduction doc id 15399 rev 9 13/157 1.5 feature details 1.5.1 e200z4 core spc564a80 devices have a high performance e200z448n3 core processor: dual issue, 32-bit power architecture embedded category cpu variable length encoding enhancements 8 kb instruction cache: 2- or 4- wa y set associative instruction cache thirty-two 64-bit general purpose registers (gprs) memory management unit (mmu) with 24-entry fully-associative translation look-aside buffer (tlb) harvard architecture: separate in struction bus and load/store bus vectored interrupt support non-maskable interrupt input critical interrupt input new ?wait for interrupt? instruction, to be used with new low power modes reservation instructions for implementing read-modify-write accesses signal processing extension (spe) apu single precision floating point (scalar and vector) nexus class 3+ debug process id manipulation for the mmu using an external tool 1.5.2 crossbar switch (xbar) the xbar multiport crossbar switch suppor ts simultaneous connec tions between five master ports and four slave ports. the crossbar supports a 32-bit address bus width and a 64-bit data bus width. the crossbar allows three concurrent transactions to occur from the master ports to any slave port but each master must access a differ ent slave. if a slave port is simultaneously requested by more than one master port, arbitration logic selects the higher priority master and grants it ownership of the slave port. all other masters requesting that slave port are stalled until the higher priority master completes its transactions. requesting masters are treated with equal priority and are granted access to a slave port in round-robin fashion, based upon the id of the last master to be granted access. the crossbar provides the following features: 5 master ports ? cpu instruction bus ? cpu data bus ?edma ?flexray ? external bus interface
introduction spc564a74l7, spc564a80b4, spc564a80l7 14/157 doc id 15399 rev 9 4 slave ports ?flash ? calibration and ebi bus ?sram ? peripheral bridge 32-bit internal address, 64-bit internal data paths 1.5.3 edma the enhanced direct memory access (edma) controller is a second-generation module capable of performing complex data movements via 64 programmable channels, with minimal intervention from the host processor. the hardware micro-architecture includes a dma engine which performs source and destination address calculations, and the actual data movement operations, along with an sram-based memory containing the transfer control descriptors (tcd) for the channels. this implementation is utilized to minimize the overall block size. the edma module provides the following features: all data movement via dual-address transfers: read from source, write to destination programmable source and destination addresses, transfer size, plus support for enhanced addressing modes transfer control descriptor organized to support two-deep, nested transfer operations an inner data transfer loop defined by a ?minor? byte transfer count an outer data transfer loop defined by a ?major? iteration count channel activation via one of three methods: ? explicit software initiation ? initiation via a channel-to-channel linki ng mechanism for continuous transfers ? peripheral-paced hardware requests (one per channel) support for fixed-priority and round-robin channel arbitration channel completion reported via optional interrupt requests one interrupt per channel, optionally asserted at completion of major iteration count error termination interrupts optionally enabled support for scatter/gather dma processing ability to suspend channel transfer s by a higher priority channel 1.5.4 interrupt controller the intc (interrupt controller) provides priority-based preemptive scheduling of interrupt requests, suitable for statically scheduled hard real-time systems. for high priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor is executing the interrupt service routine (isr) has been minimized. the intc provides a unique vector for each interrupt request source for quick determination of which isr needs to be executed. it also provides an ample number of priorities so that lower priority isrs do not delay the execution of higher priority isrs. to allow the appropriate priorities for each source of interrupt request, the priority of each interrupt request is software configurable. when multiple tasks share a resource, coherent accesses to that resource need to be supported. the intc supports the priority ceiling protocol for coherent accesses. by
spc564a74l7, spc564a80b4, spc564a80l7 introduction doc id 15399 rev 9 15/157 providing a modifiable priority mask, the priority can be raised temporarily so that all tasks which share the resource cannot preempt each other. the intc provides the following features: 9-bit vector addresses unique vector for each interrupt request source hardware connection to processor or read from register each interrupt source can assigned a specific priority by software preemptive prioritized interrupt requests to processor isr at a higher priority preempts executing isrs or tasks at lower priorities automatic pushing or popping of preempted priority to or from a lifo ability to modify the isr or ta sk priority to implement the priority ceiling protocol for accessing shared resources low latency?three clocks from receipt of interrupt request from peripheral to interrupt request to processor this device also includes a non-maskable in terrupt (nmi) pin that bypasses the intc and multiplexing logic. 1.5.5 memory protection unit (mpu) the memory protection unit (mpu) provides hardware access control for all memory references generated in a device. using preprogrammed region descriptors, which define memory spaces and their associated access rights, the mpu concurrently monitors all system bus transactions and evaluates the appropriateness of each transfer. memory references with sufficient access control rights are allowed to complete; references that are not mapped to any region descriptor or have insufficient rights are terminated with a protection error response. the mpu has these major features: support for 16 memory region descriptors, each 128 bits in size ? specification of start and end addresses provide granularity for region sizes from 32 bytes to 4 gb ? mpu is invalid at reset, thus no access restrictions are enforced ? two types of access control definitions: processor core bus master supports the traditional {read, write, execute} permissions with independent definitions for supervisor and user mode accesses; the remaining non-core bus masters (edma, flexray, and ebi 1 ) support {read, write} attributes ? automatic hardware maintenance of the region descriptor valid bit removes issues associated with maintaining a coherent image of the descriptor ? alternate memory view of the access control word for each descriptor provides an efficient mechanism to dynamically alter the access rights of a descriptor only (a) ? for overlapping region descriptors, priority is given to permission granting over access denying as this approach provides more fl exibility to system software support for two xbar slave port connections (sram and pbridge) ? for each connected xbar slave port (sram and pbridge), mpu hardware monitors every port access using the pre-programmed memory region descriptors
introduction spc564a74l7, spc564a80b4, spc564a80l7 16/157 doc id 15399 rev 9 ? an access protection error is detected if a memory reference does not hit in any memory region or the reference is flagged as illegal in all memory regions where it does hit. in the event of an access error, the xbar reference is terminated with an error response and the mpu inhibits the bus cycle being sent to the targeted slave device ? 64-bit error registers, one for each xbar slave port, capture the last faulting address, attributes, and detail information 1.5.6 fmpll the fmpll allows the user to generate high speed system clocks from a 4 mhz to 40 mhz crystal oscillator or external clock generator. further, the fmpll supports programmable frequency modulation of the system clock. the pll multiplication factor, output clock divider ratio are all software configurable. the pll has the following major features: input clock frequency from 4 mhz to 40 mhz reduced frequency divider (rfd) for reduced frequency operation without forcing the pll to relock three modes of operation ? bypass mode with pll off ? bypass mode with pll running (default mode out of reset) ? pll normal mode each of the three modes may be run with a crystal oscillator or an external clock reference programmable frequency modulation ? modulation enabled/disabled through software ? triangle wave modulation up to 100 khz modulation frequency ? programmable modulation depth (0% to 2% modulation depth) ? programmable modulation frequency dependent on reference frequency lock detect circuitry reports when the pll has achieved frequency lock and continuously monitors lock status to report loss of lock conditions clock quality module ? detects the quality of the crystal clock and causes interrupt request or system reset if error is detected ? detects the quality of the pll output clock; if error detected, causes system reset or switches system clock to crystal clock and causes interrupt request programmable interrupt request or system reset on loss of lock self-clocked mode (scm) operation 1.5.7 siu the spc564a80 siu controls mcu reset configuration, pad configuration, external interrupt, general purpose i/o (gpio), internal peripheral multiplexing, and the system reset operation. the reset configuration block contains the external pin boot configuration logic. the pad configuration block controls the static electrical characteristics of i/o pins. the a. ebi not available on all packages and is not available, as a master, for customer.
spc564a74l7, spc564a80b4, spc564a80l7 introduction doc id 15399 rev 9 17/157 gpio block provides uniform and discrete input/output control of the i/o pins of the mcu. the reset controller performs reset monitoring of internal and external reset sources, and drives the rstout pin. communication between the siu and the e200z4 cpu core is via the crossbar switch. the siu provides the following features: system configuration ? mcu reset configuration via external pins ? pad configuration control for each pad ? pad configuration control for virtual i/o via dspi serialization system reset monitoring and generation ? power-on reset support ? reset status register provides last reset source to software ? glitch detection on reset input ? software controlled reset assertion external interrupt ? rising or falling edge event detection ? programmable digital filter for glitch rejection ? critical interrupt request ? non-maskable interrupt request gpio ? centralized control of i/o and bus pins ? virtual gpio via dspi serialization (requires external deserialization device) ? dedicated input and output registers for setting each gpio and virtual gpio pin internal multiplexing ? allows serial and parallel chaining of dspis ? allows flexible selection of eqadc trigger inputs ? allows selection of interrupt requests between external pins and dspi 1.5.8 flash memory the spc564a80 provides up to 4 mb of programmable, non-volatile, flash memory. the non-volatile memory (nvm) can be used to store instructions or data, or both. the flash module includes a fetch accelerator that optimizes the performance of the flash array to match the cpu architecture. the flash module interfaces the system bus to a dedicated flash memory array controller. for cpu ?loads?, dma transfers and cpu instruction fetch, it supports a 64-bit data bus width at the system bus port, and 128- and 256-bit read data interfaces to flash memory. the module contains a prefetch controller which prefetches sequential lines of data from the flash array into the buffers. prefetch buffer hits allow no-wait responses. the flash memory provides the following features: supports a 64-bit data bus for instructio n fetch, cpu loads and dma access. byte, halfword, word and doubleword reads are supported. only aligned word and doubleword writes are supported. fetch accelerator ? architected to optimize the performance of the flash ? configurable read buffering and line prefetch support
introduction spc564a74l7, spc564a80b4, spc564a80l7 18/157 doc id 15399 rev 9 ? four-entry 256-bit wide line read buffer ? prefetch controller hardware and software configurable read and write access protections on a per-master basis interface to the flash array controller pipelined with a depth of one, allowing overlapped accesses to proceed in parallel for interleaved or pipelined flash array designs configurable access timing usable in a wide range of system frequencies multiple-mapping support and mapping-based block access timing (0-31 additional cycles) usable for emulation of other memory types software programmable block program/erase restriction control erase of selected block(s) read page size of 128 bits (four words) ecc with single-bit correction, double-bit detection program page size of 128 bits (four words) to accelerate programming ecc single-bit error corrections are visible to software minimum program size is two consecutive 32-bit words, aligned on a 0-modulo-8 byte address, due to ecc embedded hardware program and erase algorithm erase suspend, program suspend and erase-suspended program shadow information stored in non-volatile shadow block independent program/erase of the shadow block 1.5.9 bam the bam (boot assist module) is a block of read-only memory that is programmed once by st and is identical for all spc564a80 mcus. the bam program is executed every time the mcu is powered-on or reset in normal mode. the bam supports different modes of booting. they are: booting from internal flash memory serial boot loading (a program is downloaded into ram via esci or the flexcan and then executed) booting from external memory on external bus the bam also reads the reset configuration half word (rchw) from internal flash memory and configures the spc564a80 hardware accordingly. the bam provides the following features: sets up mmu to cover all resources and ma pping of all physical addresses to logical addresses with minimum address translation sets up mmu to allow user boot code to execute as either power architecture embedded category (default) or as vle code location and detection of user boot code automatic switch to serial boot mode if internal flash is blank or invalid supports user programmable 64-bit password protection for serial boot mode supports serial bootloading via flexcan bus and esci using standard protocol supports serial bootloading via flexcan bus and esci with auto baud rate sensing supports serial bootloading of either power architecture code (default) or vle code
spc564a74l7, spc564a80b4, spc564a80l7 introduction doc id 15399 rev 9 19/157 supports booting from calibration bus interface supports censorship protection for internal flash memory provides an option to enable the core watchdog timer provides an option to disable the system watchdog timer 1.5.10 emios the emios timer module prov ides the capability to gene rate or measure events in hardware. the emios module features include: twenty-four 24-bit wide channels 3 channels? internal timebases can be shared between channels 1 timebase from etpu2 can be imported and used by the channels global enable feature for all emios and etpu timebases dedicated pin for each channel (not available on all package types) each channel (0?23) supports the following functions: general-purpose input/output (gpio) single-action input capture (saic) single-action output compare (saoc) output pulse-width modulation buffered (opwmb) input period measurement (ipm) input pulse-width measurement (ipwm) double-action output compare (daoc) modulus counter buffered (mcb) output pulse width and frequency modulation buffered (opwfmb) 1.5.11 etpu2 the etpu2 is an enhanced co-processor designed for timing control. operating in parallel with the host cpu, the etpu2 processes instructions and real-time input events, performs output waveform generation, and accesses shared data without host intervention. consequently, for each timer event, the host cpu setup and service times are minimized or eliminated. a powerful timer subsystem is formed by combining the etpu2 with its own instruction and data ram. high-level asse mbler/compiler and do cumentation allows customers to develop their own functions on the etpu2. spc564a80 devices feature the second generation of the etpu, called etpu2. enhancements of the etpu2 over the standard etpu include: the timer counter (tcr1), channel logic and digital filters (both channel and the external timer clock input [tcrclk]) now have an option to run at full system clock speed or system clock / 2. channels support unordered transitions: transition 2 can now be detected before transition 1. related to this enhancement, the transition detection latches (tdl1 and tdl2) can now be independently negated by microcode. a new user programmable channel mode has been added: the blocking, enabling, service request and capture characteristics of this channel mode can be programmed via microcode.
introduction spc564a74l7, spc564a80b4, spc564a80l7 20/157 doc id 15399 rev 9 microinstructions now provide an option to issue interrupt and data transfer requests selected by channel. they can also be requested simultaneously at the same instruction. channel flags 0 and 1 can now be tested for branching, in addition to selecting the entry point. channel digital filters can be bypassed. the etpu2 includes these distinctive features: 32 channels; each channel associated with one input and one output signal ? enhanced input digital filters on the input pins for improved noise immunity ? identical, orthogonal channels: each channel can perform any time function. each time function can be assigned to more than one channel at a given time, so each signal can have any functionality. ? each channel has an event mechanism which supports single and double action functionality in various combinations. it includes two 24-bit capture registers, two 24-bit match registers, 24-bit greater-equal and equal-only comparators. ? input and output signal states visible from the host 2 independent 24-bit time bases for channel synchronization: ? first time base clocked by system clock with programmable pre scale division from 2 to 512 (in steps of 2), or by output of second time base prescaler ? second time base counter can work as a continuous angle counter, enabling angle based applications to match angle instead of time ? both time bases can be exported to the emios timer module ? both time bases visible from the host event-triggered microengine: ? fixed-length instruction execution in two-system-clock microcycle ? 14 kb of code memory (scm) ? 3 kb of parameter (data) ram (spram) ? parallel execution of data memory, alu, channel control and flow control sub- instructions in se lected combinations ? 32-bit microengine registers and 24-bit wide alu, with 1 microcycle addition and subtraction, absolute value, bitwise logical operations on 24-bit, 16-bit, or byte operands, single-bit manipulation, shift operations, sign extension and conditional execution ? additional 24-bit multiply /mac/divide unit which supports all signed/unsigned multiply/mac combinations , and unsigned 24-bit divide. the mac/divide unit works in parallel with the regular microcode commands. resource sharing features support channel use of common channel registers, memory and microengine time: ? hardware scheduler works as a ?task management? unit, dispatching event service routines by predefined, host-configured priority ? automatic channel context switch when a ?task switch? occurs, that is, one function thread ends and another begins to servic e a request from other channel: channel- specific registers, flags and parameter base address are automatically loaded for the next serviced channel
spc564a74l7, spc564a80b4, spc564a80l7 introduction doc id 15399 rev 9 21/157 ? spram shared between host cpu and etpu2, supporting communication either between channels and host or inter-channel ? hardware implementation of four semaphores support coherent parameter sharing between both etpu engines ? dual-parameter coherency hardware support allows atomic access to two parameters by host test and development support features: ? nexus class 1 debug, supporting single-step execution, arbitrary microinstruction execution, hardware breakpoints and watchpoints on several conditions ? software breakpoints ? scm continuous signature-check built-in self test (misc - multiple input signature calculator), runs concurrently with etpu2 normal operation 1.5.12 reaction module the reaction module provides the ability to mo dulate output signals to manage cl osed loop control without cpu assistance. it works in conjunction with the eqadc and etpu2 to increase system performance by removing the cpu from the cu rrent control loop. the reaction module has the following features: six reaction channels each channel output is a bus of three sign als, providing ability to control 3 inputs. each channel can implement a peak and hold waveform, making it possible to implement up to six independent peak and hold control channels target applications include solenoid control for direct injection systems and valve control in automatic transmissions 1.5.13 eqadc the enhanced queued analog to digital converter (eqadc) block provides accurate and fast conversions for a wide range of applications. the eqadc provides a parallel interface to two on-chip analog to digital converters (adc), and a single master to single slave serial interface to an off-chip external device. both on-chip adcs have access to all the analog channels. the eqadc prioritizes and transfers commands from six command conversion command ?queues? to the on-chip adcs or to the external device. the block can also receive data from the on-chip adcs or from an off-chip external device into the six result queues, in parallel, independently of the command queues. the six command queues are prioritized with queue_0 having the highest priority and queue_5 the lowest. queue_0 also has the added ability to bypass all buffering and queuing and abort a currently running conv ersion on either adc and start a queue_0 conv ersion. this means that queue_0 will always have a deterministic time from trigger to start of conversion, irrespective of what tasks the adcs were performing when the trigger occurred. the eqadc supports software and external hardware triggers from other blocks to initiate transfers of commands from the queues to the on-chip adcs or to the external device. it also monitors the fullness of command queues and result queues, and accordingly generates dma or interrupt requests to control data movement between the queues and the system memory, which is external to the eqadc. the adcs also support features designed to allow the direct connection of high impedance acoustic sensors that might be used in a system for detecting engine knock. these features
introduction spc564a74l7, spc564a80b4, spc564a80l7 22/157 doc id 15399 rev 9 include differential inputs; integrated variable gain amplifiers for increasing the dynamic range; programmable pull-up and pull-down resistors for biasing and sensor diagnostics. the eqadc also integrates a programmable decimation filter capable of taking in adc conversion results at a high rate, passing them through a hardware low pass filter, then down-sampling the output of the filter and feeding the lower sample rate results to the result fifos. this allows the adcs to sample the sens or at a rate high enough to avoid aliasing of out-of-band noise; while providing a reduced sample rate output to minimize the amount dsp processing bandwidth required to fully process the digitized waveform. the eqadc provides the following features: dual on-chip adcs ?2 ? 12-bit adc resolution ? programmable resolution for increased conversion speed (12-bit, 10-bit, 8-bit) 12-bit conversion time: 938 ns (1 m sample/sec) 10-bit conversion time: 813 ns (1.2 m sample/second) 8-bit conversion time: 688 ns (1.4 m sample/second) ? up to 10-bit accuracy at 500 ksample/s and 8-bit accuracy at 1 msample/s ? differential conversions ? single-ended signal range from 0 to 5 v ? variable gain amplifiers on differential inputs ( ? 1, ? 2, ? 4) ? sample times of 2 (default), 8, 64 or 128 adc clock cycles ? provides time stamp information when requested ? allows time stamp information relative to etpu clock sources, such as an angle clock ? parallel interface to eqadc cfifos and rfifos ? supports both right-justified unsigned and signed formats for conversion results 40 single-ended input channels, expandable to 56 channels with external multiplexers (supports four external 8-to-1 muxes) 8 channels can be used as 4 pairs of differential analog input channels differential channels include variable gain amplifier for improved dynamic range differential channels include programmable pull-up and pull-down resistors for biasing and sensor diagnostics (200 k ??? 100 k ??? 5k ?? additional internal channels for monitoring voltages (such as core voltage, i/o voltage, lvi voltages, etc.) inside the device an internal bandgap reference to allow absolute voltage measurements silicon die temperature sensor ? provides temperature of silicon as an analog value ? read using an internal adc analog channel ? may be read with either adc 2 decimation filters ? programmable decimation factor (1 to 16) ? selectable iir or fir filter ? up to 4th order iir or 8th order fir ? programmable coefficients
spc564a74l7, spc564a80b4, spc564a80l7 introduction doc id 15399 rev 9 23/157 ? saturated or non-saturated modes ? programmable rounding (convergent; two?s complement; truncated) ? prefill mode to precondition the filt er before the sa mple window opens ? supports multiple cascadin g decimation filters to impl ement more complex filter designs ? optional absolute integrators on the output of decimation filters full duplex synchronous serial interface to an external device ? free-running clock for use by an external device ? supports a 26-bit message length priority based queues ? supports six queues with fixed priority. when commands of distinct queues are bound for the same adc, the higher priority queue is always served first ? queue_0 can bypass all prioritization, buffering and abort current conversions to start a queue_0 conversion a deterministic time after the queue trigger ? supports software and hardware trigger modes to arm a particular queue ? generates interrupt when command coherency is not achieved external hardware triggers ? supports rising edge, falling edge, high level and low level triggers ? supports configurable digital filter 1.5.14 dspi the deserial serial peripheral interface (dspi) block provides a synchronous serial interface for communication between the spc564a80 mcu and external devices. the dspi supports pin count reduction through serialization and deserialization of etpu and emios channels and memory-mapped registers. the channels and register content are transmitted using a spi-like protocol. this spi-like protocol is completely configurable for baud rate, polarity and phase, frame length, chip select assertion, etc. each bit in the frame may be configured to serialize either etpu channels, emios channels or gpio signals. the dspi can be configured to serialize data to an external device that implements the microsecond bus protocol. there are three identical dspi blocks on the spc564a80 mcu. the dspi pins support 5 v logic levels or low voltage differe ntial signalling (lvds) to improve high speed operation. dspi module features include: selectable lvds pads working at 40 mhz for sout and sck pins for dspi_b and dspi_c 3 sources of serialized data: etpu_a, emios output channels and memory-mapped register in the dspi 4 destinations for deserialized data: etpu_a and emios input channels, siu external interrupt input request, memory-mapped register in the dspi 32-bit dsi and tsb modes require 32 pcr registers, 32 gpo and gpi registers in the siu to select either gpio, etpu or emios bits for serialization the dspi module can generate and check parity in a serial frame
introduction spc564a74l7, spc564a80b4, spc564a80l7 24/157 doc id 15399 rev 9 1.5.15 esci three enhanced serial communications interface (esci) modules provide asynchronous serial communications with peripheral devices and other mcus, and include support to interface to local interconnect network (lin) slave devices. each esci block provides the following features: full-duplex operation standard mark/space non-return-to-zero (nrz) format 13-bit baud rate selection programmable 8-bit or 9-bit, data format programmable 12-bit or 13-bit data format for timed serial bus (tsb) configuration to support the microsecond bus standard automatic parity generation lin support ? autonomous transmission of entire frames ? configurable to support all revisions of the lin standard ? automatic parity bit generation ? double stop bit after bit error ? 10- or 13-bit break support separately enabled transmitter and receiver programmable transmitter output parity 2 receiver wake-up methods: ? idle line wake-up ? address mark wake-up interrupt-driven operation with flags receiver framing error detection hardware parity checking 1/16 bit-time noise detection dma support for both transmit and receive data ? global error bit stored with receive data in system ram to allow post processing of errors 1.5.16 flexcan the spc564a80 mcu includes three controller area network (flexcan) blocks. the flexcan module is a communication controller implementing the can protocol according to bosch specification version 2.0b. the can protoc ol was designed to be used primarily as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in the emi environment of a vehicle, cost-effectiveness and required bandwidth. each flexcan module contains 64 message buffers.
spc564a74l7, spc564a80b4, spc564a80l7 introduction doc id 15399 rev 9 25/157 the flexcan modules provide the following features: full implementation of the can protocol specification, version 2.0b ? standard data and remote frames ? extended data and remote frames ? zero to eight bytes data length ? programmable bit rate up to 1 mbit/s content-related addressing 64 message buffers of zero to eight bytes data length individual rx mask register per message buffer each message buffer configurable as rx or tx, all supporting standard and extended messages includes 1088 bytes of embedded memory for message buffer storage includes 256-byte memory for storing individual rx mask registers full featured rx fifo with storage capacity for six frames and internal pointer handling powerful rx fifo id filtering, capable of matching incoming ids against 8 extended, 16 standard or 32 partial (8 bits) id s, with individual masking capability selectable backwards compatibilit y with previous flexcan versions programmable clock source to the can protocol interface, either system clock or oscillator clock listen only mode capability programmable loop-back mode supporting self-test operation 3 programmable mask registers programmable transmit-first scheme: lowest id, lowest buffer number or highest priority time stamp based on 16-bit free-running timer global network time, synchronized by a specific message maskable interrupts warning interrupts when the rx and tx error counters reach 96 independent of the transmission medium (an external transceiver is assumed) multi-master concept high immunity to emi short latency time due to an arbitration scheme for high-priority messages low power mode, with programmable wake-up on bus activity
introduction spc564a74l7, spc564a80b4, spc564a80l7 26/157 doc id 15399 rev 9 1.5.17 flexray the spc564a80 includes one dual-channel flexray module that implements the flexray communications system protocol specification, version 2.1 rev a. features include: single channel support flexray bus data rates of 10 mbit/s, 8 mbit/s, 5 mbit/s, and 2.5 mbit/s supported 128 message buffers, each configurable as: ? receive message buffer ? single buffered transmit message buffer ? double buffered transmit message buffer (combines two single buffered message buffer) 2 independent receive fifos ? 1 receive fifo per channel ? up to 255 entries for each fifo ecc support 1.5.18 system timers the system timers include two distinct types of system timer: periodic interrupts/triggers using the periodic interrupt timer (pit) operating system task monitors using the system timer module (stm) periodic interrupt timer (pit) the pit provides five independent timer channels, capable of producing periodic interrupts and periodic triggers. the pit has no external input or output pins and is intended to provide system ?tick? signals to the operating system, as well as periodic triggers for eqadc queues. of the five channels in the pit, four are clocked by the system clock and one is clocked by the crystal clock. this one channel is also re ferred to as real-time interrupt (rti) and is used to wake up the device from low power stop mode. the following features are implemented in the pit: 5 independent timer channels each channel includes 32-bit wide down counter with automatic reload 4 channels clocked from system clock 1 channel clocked from crystal clock (wake-up timer) wake-up timer remains active when system stop mode is entered; used to restart system clock after predefined time-out period each channel optionally able to generate an interrupt request or a trigger event (to trigger eqadc queues) when timer reaches zero system timer module (stm) the system timer module (stm) is designed to implement the software task monitor as defined by autosar (b) . it consists of a single 32-bit counter, clocked by the system clock, b. autosar: automotive open system architecture (see www.autosar.org)
spc564a74l7, spc564a80b4, spc564a80l7 introduction doc id 15399 rev 9 27/157 and four independent timer comparators. these comparators produce a cpu interrupt when the timer exceeds the programmed value. the following features are implemented in the stm: one 32-bit up counter with 8-bit prescaler four 32-bit compare channels independent interrupt source for each channel counter can be stopped in debug mode 1.5.19 software watchdog timer (swt) the software watchdog timer (swt) is a second watchdog module to complement the standard power architecture watchdog integrated in the cpu core. the swt is a 32-bit modulus counter, clocked by the system clock or the crystal clock, that can provide a system reset or interrupt request when the correct software key is not written within the required time window. the following features are implemented: 32-bit modulus counter clocked by system clock or crystal clock optional programmable watchdog window mode can optionally cause system reset or interrupt request on timeout reset by writing a software key to memory mapped register enabled out of reset configuration is protected by a software key or a write-once register 1.5.20 cyclic redundanc y check (crc) module the crc computing unit is dedicated to the computation of crc off-loading the cpu. the crc features: support for crc-16-ccitt (x25 protocol): ?x 16 + x 12 + x 5 + 1 support for crc-32 (ethernet protocol): ?x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1 zero wait states for each write/read operations to the crc_cfg and crc_inp registers at the maximum frequency 1.5.21 error correctio n status module (ecsm) the ecsm provides a myriad of miscellaneous control functions regarding program-visible information about the platform configuration and revision levels, a reset status register, a software watchdog timer, wakeup control for exiting sleep modes, and information on platform memory errors reported by error-correcting codes and/or generic access error information for certain processor cores.
introduction spc564a74l7, spc564a80b4, spc564a80l7 28/157 doc id 15399 rev 9 the error correction status module supports a number of miscellaneous control functions for the platform. the ecsm includes these features: registers for capturing information on platform memory errors if error-correcting codes (ecc) are implemented for test purposes, optional registers to specify the generation of double-bit memory errors are enabled on the spc564a80. the sources of the ecc errors are: flash sram peripheral ram (flexray, can, etpu2 parameter ram) 1.5.22 external bus interface (ebi) the spc564a80 device features an external bus interface that is available in pbga324 and calibration packages. the ebi supports operation at frequencies of system clock /1, /2 and /4, with a maximum frequency support of 80 mhz. customers runn ing the device at 120 mhz or 132 mhz will use the /2 divider, giving an ebi frequency of 60 mhz or 66 mhz. customers running the device at 80 mhz will be able to use the /1 di vider to have the ebi run at the full 80 mhz frequency. features include: 1.8 v to 3.3 v 10% i/o (1.6 v to 3.6 v) memory controller with support for various memory types 16-bit data bus, up to 22-bit address bus pin muxing included to support 32-bit muxed bus selectable drive strength configurable bus speed modes bus monitor configurable wait states 1.5.23 calibration ebi the calibration ebi controls data transfer across the crossbar switch to/from memories or peripherals attached to the calibration tool connector in the calibration address space. the calibration ebi is only availa ble in the calibration tool. features include: 1.8 v to 3.3 v 10% i/o (1.6 v to 3.6 v) memory controller supports various memory types 16-bit data bus, up to 22-bit address bus pin muxing supports 32-bit muxed bus selectable drive strength configurable bus speed modes bus monitor configurable wait states
spc564a74l7, spc564a80b4, spc564a80l7 introduction doc id 15399 rev 9 29/157 1.5.24 power manageme nt controller (pmc) the power management controller contains circuitry to generate the internal 3.3 v supply and to control the regulation of 1.2 v supply with an external npn ballast transistor. it also contains low voltage inhibit (lvi) and power-on reset (por) circuits for the 1.2 v supply, the 3.3 v supply, the 3.3 v/5 v supply of the clos est i/o segment (vddeh1) and the 5 v supply of the regulators (vddreg). 1.5.25 nexus port controller the npc (nexus port controller) block prov ides real-time nexus class3+ development support capabilities for the spc564a80 power architecture-based mcu in compliance with the ieee-isto 5001-2003 and 20 10 standards. mdo port widths of 4 pins and 12 pins are available in all packages. 1.5.26 jtag the jtagc (jtag controller) block provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode. testing is performed via a boundary scan technique, as defined in the ieee 1149.1-2001 standard. all data input to and output from the jtagc block is communicated in serial format. the jtagc block is compliant with the ieee 1149.1-2001 standard and su pports the following features: ieee 1149.1-2001 test access port (tap) interface 4 pins (tdi, tms, tck, and tdo) a 5-bit instruction register that supports the following ieee 1149.1-2001 defined instructions: ? bypass, idcode, extest, sample, sample/preload, highz, clamp a 5-bit instruction register that supports the additional followin g public instructions: ? access_aux_tap_npc ? access_aux_tap_once ? access_aux_tap_etpu ? access_censor 3 test data registers to support jtag boundary scan mode ? bypass register ? boundary scan register ? device identification register a tap controller state machine that controls the operation of the data registers, instruction register and associated circuitry censorship inhibit register ? 64-bit censorship password register ? if the external tool writes a 64-bit password that matches the serial boot password stored in the internal flash shadow row, censorship is disabled until the next system reset. 1.5.27 development tr igger semaphore (dts) spc564a80 devices include a system development feature, the development trigger semaphore (dts) module, that enables software to signal an external tool by driving a persistent (affected only by reset or an external tool) signal on an external device pin. there
introduction spc564a74l7, spc564a80b4, spc564a80l7 30/157 doc id 15399 rev 9 is a variety of ways this module can be used, including as a component of an external real- time data acquisition system 1.6 spc564a80 series architecture 1.6.1 block diagram figure 1 shows a top-level block diagram of the spc564a80 series.
spc564a74l7, spc564a80b4, spc564a80l7 introduction doc id 15399 rev 9 31/157 figure 1. spc564a80 series block diagram adc ? analog to digital converter adci ? adc interface amux ? analog multiplexer bam ? boot assist module crc ? cyclic redundancy check unit dec ? decimation filter dts ? development trigger semaphore dspi ? deserial/serial peripheral interface ebi ? external bus interface ecsm ? error correction status module edma ? enhanced direct memory access emios ? enhanced modular input output system esci ? enhanced serial communications interface etpu2 ? second gen. enhanced time processing unit flexcan ? controller area network (flexcan) fmpll ? frequency-modulated phase locked loop jtag ? ieee 1149.1 test controller mmu ? memory management unit mpu ? memory protection unit pmc ? power management controller pit ? periodic interrupt timer rcosc ? low-speed rc oscillator reacm ? reaction module siu ? system integration unit spe ? signal processing extension sram ? static ram stm ? system timer module swt ? software watchdog timer vga ? variable gain amplifier vle ? variable length (instruction) encoding xosc ? xtal oscillator legend emios 24 channel 3 kb data ram 14 kb code ram etpu2 32 channel temp sens adci dec x2 vga adc adc amux 4 mb flash 192 kb sram mpu crossbar switch interrupt controller edma 64 channel spe vle mmu 8 kb i-cache power architecture e200z4 tm jtag nexus ieee-isto 5001-2003/2010 flexray ext. bus interface cal bus interface flexcan ? 3 nexus class 3+ nexus i/o bridge fmpll crc bam pmc stm pit swt siu analog pll rcosc xosc voltage regulator standby regulator with switch dspi ? 3 esci ? 3 m4 m0 m6 m7 s0 s2 s7 s1 m1 reacm dts class 1 ecsm
introduction spc564a74l7, spc564a80b4, spc564a80l7 32/157 doc id 15399 rev 9 1.6.2 block summary ta bl e 3 summarizes the functions of the bl ocks present on the spc564a80 series microcontrollers. table 3. spc564a80 series block summary block function boot assist module (bam) block of read-only memory containing executable code that searches for user-supplied boot code and, if none is found, executes the bam boot code resident in device rom. calibration bus interface transfers data across the crossbar switch to/from peripherals attached to the calibration tool connector. controller area network (flexcan) supports the standard can communications protocol. crossbar switch (xbar) internal busmaster. cyclic redundancy check (crc) crc checksum generator. deserial serial peripheral interface (dspi) provides a synchronous serial interface for communication with external devices. e200z4 core executes programs and interrupt handlers. enhanced direct memory access (edma) performs complex data movements with minimal intervention from the core. enhanced modular in put-output system (emios) provides the functionality to generate or measure events. enhanced queued analog-to-digital converter (eqadc) provides accurate and fast conversions for a wide range of applications. enhanced serial communication interface (esci) provides asynchronous serial communication capability with peripheral devices and other microcontroller units. enhanced time processor unit (etpu2) second-generation co-processor processes real-time input events, performs output waveform generation, and accesses shared data without host intervention. error correction stat us module (ecsm) the error correction status module supports a number of miscellaneous control functions for the platform, and includes registers for capturing information on platform memory errors if error- correcting codes (ecc) are implemented external bus interface (ebi) enables expansion of internal bus to enable connection of external memory or peripherals. flash memory provides storage for program code, constants, and variables. flexray provides high-speed distributed control for advanced automotive applications. interrupt controller (intc) provides priority-bas ed preemptive scheduling of interrupt requests. jtag controller provides the means to test chip functionality and connectivity while remaining transparent to system logi c when not in test mode. memory protection unit (mpu) provides hardware access control for all memory references generated. nexus port controller (npc) provides real-time development support capabilities in compliance with the ieee-isto 5001-2003 standard.
spc564a74l7, spc564a80b4, spc564a80l7 introduction doc id 15399 rev 9 33/157 reaction module (reacm) works in conjunction with the eqa dc and etpu2 to increase system performance by removing the cpu from the current control loop. system integration unit (siu) controls mcu reset configuration, pad configuration, external interrupt, general purpose i/o (gpio), internal peripheral multiplexing, and the system reset operation. static random-access memory (sram) provides stor age for program code, constants, and variables. system timers includes periodic interrupt timer with real-time interrupt; output compare timer and system watchdog timer. temperature sensor provides the temperature of the device as an analog value. table 3. spc564a80 series block summary (continued) block function
pinout and signal description spc 564a74l7, spc564a80b4, spc564a80l7 34/157 doc id 15399 rev 9 2 pinout and signal description this section contains the pinouts for all production packages for the spc564a80 family of devices. caution: any pins labeled ?nc? are to be left unconnec ted. any connection to an external circuit or voltage may cause unpredictable device behavior or damage.
spc564a74l7, spc564a80b4, spc564a80l7 pinout and signal description doc id 15399 rev 9 35/157 2.1 lqfp176 pinout figure 2. 176-pin lqfp pinout (top view) 176-pin lqfp vdd an[37] an[36] an[21] an[0] (dan0+) an[1] (dan0-) an[2] (dan1+) an[3] (dan1-) an[4] (dan2+) an[5] (dan2-) an[6] (dan3+) an[7] (dan3-) refbypc vrh vrl an[22] an[23] an[24] an[25] an[27] an[28] an[30] an[31] an[32] an[33] an[34] an[35] vdd an[12] / ma[0] / etpua19_o /sds an[13] / ma[1] / etpua21_o / sdo an[14] / ma[2] / etpua27_o / sdi an[15] / fck / etpua29_o gpio[207] etrig1 gpio[206] etrig0 dspi_d_sin / gpio[99] dspi_d_sck / gpio[98] vss mdo9 / etpua25_o / gpio[80] vddeh7b mdo8 / etpua21_o / gpio[79] mdo7 / etpua19_o / gpio[78] mdo6 / etpua13_o / gpio[77] mdo10 / etpua27_o / gpio[81] vss vdd etpua13 / dspi_b_pcs[3] / gpio[127] etpua12 / dspi_b_pcs[1] / rch4_c / gpio[126] etpua11 / etpua23_o / rch4_b / gpio[125] etpua10 / etpua22_o / rch1_c /gpio[124] etpua9 / etpua21_o / rch1_b / gpio[123] etpua8 / etpua20_o / dspi_b_sout_lvds+ / gpio[122] etpua7 / etpua19_o / dspi_b_sout_lvds- / etpua6_o / gpio[121] etpua6 / etpua18_o / dspi_b_sck_lvds+ / fr_b_rx / gpio[120] etpua5 / etpua17_o / dspi_b_sck_lvds- / fr_b_tx_en/ gpio[119] vddeh4a etpua4 / etpua16_o / fr_b_tx / gpio[118] vss etpua3 / etpua15_o / gpio[117] etpua2 / etpua14_o / gpio[116] etpua1 / etpua13_o / gpio[115] etpua0 / etpua12_o / etpua19_o / gpio[114] vdd emios0 / etpua0 / etpua25_o / gpio[179] emios1 / etpua1_o / gpio[180] emios2 / etpua2_o / rch2_b / gpio[181] emios3 / etpua3_o /gpio[182] emios4 / etpua4_o / rch2_c / gpio[183] emios6 / etpua6_o / gpio[185] emios7 / etpua7_o / gpio[186] emios8 / etpua8_o / sci_b_tx / gpio[187] emios9 / etpua9_o / sci_b_rx / gpio[188] vss emios10 / dspi_d_pcs3 / rch3_b / gpio[189] vddeh4b emios11 / dspi_d_pcs4 / rch3_c / gpio[190] emios12 / dspi_c_sout / etpua27_o / gpio[191] emios13 / dspi_d_sout / gpio[192] emios14 / irq [0] / etpua29_o / gpio[193] emios15 / irq [1] / gpio[194] emios23 / gpio[202] can_a_tx / sci_a_tx / gpio[83] can_a_rx / sci_a_rx / gpio[84] pllref / irq [4]/etrig[2] / gpio[208] sci_b_rx / dspi_d_pcs5 / gpio[92] bootcfg1 / irq [3] / etrig[3] / gpio[212] wkpcfg / nmi / dspi_b_sout / gpio[213] sci_b_tx / dspi_d_pcs1 / gpio[91] can_b_tx / dspi_c_pcs3 / sci_c_tx / gpio[85] an[18] an[17] an[16] an[11] / anz an[9] / anx vdda vssa an[39] an[8] / anw vddreg vrcctl vstby vrc33 mcko vss nc mdo[0] mdo[1] mdo[2] mdo[3] (see signal details, pin 21) (see signal details, pin 22) (see signal details, pin 23) (see signal details, pin 24) (see signal details, pin 25) (see signal details, pin 26) (see signal details, pin 27) (see signal details, pin 28) vss (see signal details, pin 30) vddeh1a (see signal details, pin 32) vdd (see signal details, pin 34) (see signal details, pin 35) (see signal details, pin 36) (see signal details, pin 37) (see signal details, pin 38) (see signal details, pin 39) (see signal details, pin 40) vddeh1b (see signal details, pin 42) vss nic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 signal details: pin 21: etpua31 / dspi_c_ pcs[4] / etpua13_o / gpio[145] pin 22: etpua30 / dspi_c_ pcs[3] / etpua11_o / gpio[144] pin 23: etpua29 / dspi_c_pcs[2] / rch5_c / gpio[143] pin 24: etpua28 / dspi_c_ pcs[1] / rch5_b / gpio[142] pin 25: etpua27 / irq [15] / dspi_c_sout_lvds+ / soutb / gpio[141] pin 26: etpua26 / irq [14] / dspi_c_ sout_lvds- / gpio[140] pin 27: etpua25 / irq [13] / dspi_c_ sck_lvds+ / gpio[139] pin 28: etpua24 / irq [12] / dspi_c_ sck_lvds- / gpio[138] pin 30: etpua23 / irq [11] / etpua21_o / fr_a_tx_en / gpio[137] pin 32: etpua22 / irq [10] / etpua17_o / gpio[136] pin 34: etpua21 / irq[9] / rch0_c / fr_a_rx / gpio[135] pin 35: etpua20 / irq[8] / rch0_b / fr_a_tx / gpio[134] pin 36: etpua19 / dspi_d_ pcs[4] / rch5_a / gpio[133] pin 37: etpua18 / dspi_d_ pcs[3] / rch4_a / gpio[132] pin 38: etpua17 / dspi_d_ pcs[2] / rch3_a / gpio[131] pin 39: etpua16 / dspi_d_ pcs[1] / rch2_a / gpio[130] pin 40: etpua15 / dspi_b_ pcs[5] / rch1_a / gpio[129] pin 42: etpua14 / dspi_b_ pcs[4] / etpua9_o / rch0_a / gpio[128] note: pin 96 (vss) should be tied low. vdd tms tdi mdo5 / etpua4_o / gpio[76] tck vss mdo4 / etpua2_o / gpio[75] vddeh7a mdo11 / etpua29_o / gpio[82] tdo gpio[219] jcomp evto nc mseo [0] mseo [1] evti vss dspi_b_pcs[3] / dspi_c_sin / gpio[108] dspi_b_sout / dspi_c_pcs[5] / gpio[104] dspi_b_sin / dspi_c_pcs[2] / gpio[103] dspi_b_pcs[0] / dspi_d_pcs[2] / gpio[105] vddeh6b dspi_b_pcs[1] / dspi_d_pcs[0] / gpio[106] vss dspi_b_pcs[2] / dspi_c_sout / gpio[107] dspi_b_sck / dspi_c_pcs[1] / gpio[102] dspi_b_pcs[4] / dspi_c_sck / gpio[109] dspi_b_pcs[5] / dspi_c_pcs[0] / gpio[110] vdd rstout can_c_tx / dspi_d_pcs3 / gpio[87] sci_a_tx / emios13 / gpio[89] sci_a_rx / emios15 / gpio[90] can_c_rx / dspi_d_pcs4 / gpio[88] reset vss vddeh6a vss xtal extal / extclk vddpll vss can_b_rx / dspi_c_pcs[4] / sci_c_rx / gpio[86]
spc564a74l7, spc564a80b4, spc564a80l7 pinout and signal description doc id 15399 rev 9 36/157 2.2 lbga208 ballmap figure 3. 208-pin lbga package ballmap (viewed from above) 123 4 56 7 8 9 10 1112 13141516 a vss an9 an11 vdda1 vssa1 an1 an5 vrh vrl an27 vssa0 an12-sds mdo2 mdo0 vrc33 vss a b vdd vss an8 an21 an0 an4 refbypc an22 an25 an28 vdda0 an13-sdo mdo3 mdo1 vss vdd b c vstby vdd vss an17 an34 an16 an3 an7 an23 a n32 an33 an14-sdi an15-fck vss mseo0 tck c d vrc33 an39 vdd vss an18 an2 an6 an24 an30 an31 an35 vddeh7 vss tms evto nc d e etpua30 etpua31 an37 vdd nc tdi evti mseo1 e f etpua28 etpua29 etpua26 an36 vddeh6ab tdo mcko jcomp f g etpua24 etpua27 etpua25 etpua21 vss vss vss vss dspi_b_ sout dspi_b_ pcs3 dspi_b_ sin dspi_b_ pcs0 g h etpua23 etpua22 etpua17 etpua18 vss vss vss vss gpio99 dspi_b_ pcs4 dspi_b_ pcs2 dspi_b_ pcs1 h j etpua20 etpua19 etpua14 etpua13 vss vss vss vss dspi_b_ pcs5 sci_a_tx gpio98 dspi_b_ sck j k etpua16 etpua15 etpua7 vddeh1ab vss vss vss vss can_c_tx sci_a_r x rstout vddreg k l etpua12 etpua11 etpua6 tcrclka sci_b_tx can_c_ rx wkpcfg reset l m etpua10 etpua9 etpua1 etpua5 sci_b_rx pllref bootcfg1 vss m n etpua8 etpua4 etpua0 vss vdd vrc33 emios2 emios10 vddeh4ab emios12 mdo7_ etpua19_ o vrc33 vss (1) vrcctl nc extal n p etpua3 etpua2 vss vdd gpio207 nc emios6 emios8 mdo11_ etpua29_ o mdo4_ etpua2_o mdo8_ etpua21_ o can_a_tx vdd vss nc xtal p r nc vss vdd gpio206 emios4 emios3 emios9 emios11 emios14 mdo10_ etpua27_ o emios23 can_a_rx can_b_rx vdd vss vddpll r t vss vdd nc emios0 emios1 gpio219 mdo9_ etpua25_ o emios13 emios15 mdo5_ etpua4_o mdo6_ etpua13_ o can_b_tx vdde5 engclk vdd vss t 123 4 56 7 8 9 10 1112 13141516 1. this pin (n13) should be tied low.
pinout and signal description spc564a74l7, spc564a80b4, spc564a80l7 37/157 doc id 15399 rev 9 2.3 pbga324 ballmap figure 4. 324-pin pbga package ballmap (northwest, viewed from above) 1234567891011 a vss vdd vstby an37 an11 vdda0 vssa0 an1 an5 vrh vrl b vrc33 vss vdd an36 an39 an19 an16 an0 an4 refbypc an23 c etpua30 etpua31 vss vdd an38 an17 an20 an21 an3 an7 an22 d etpua28 etpua29 etpua26 vss vdd an8 anw an9 an10 any an18 an2 an6 e etpua24 etpua27 etpua25 etpua21 f etpua23 etpua22 etpua17 etpua18 g etpua20 etpua19 etpua14 etpua13 h etpua16 etpua15 etpua10 vddeh1ab j etpua12 etpua11 etpua6 etpua9 vss vss vss k etpua8 etpua7 etpua2 etpua5 vss vss vss l etpua4 etpua3 etpua0 etpua1 vss vss vss
spc564a74l7, spc564a80b4, spc564a80l7 pinout and signal description doc id 15399 rev 9 38/157 figure 5. 324-pin pbga package ballmap (southwest, viewed from above) m bdip tcrclka cs1 cs0 vdde2 vdde2 vss ncs3 cs2 we1 we0 vss vss vdde2 p addr16 addr17 rd_wr vrc33 vss vss vdde2 r addr18 addr19 vdde-eh ta t addr20 addr21 addr12 ts u addr22 addr23 addr13 addr14 v addr24 addr25 addr15 addr31 w addr26 vdde-eh addr30 vss vdd vdde2 vrc33 vdde2 data11 data12 data14 y addr28 addr27 vss vdd vdde2 data8 data9 data10 gpio207 data13 data15 aa addr29 vss vdd vdde2 data1 vdde2 gpio206 data5 data7 vdde2 emios3 ab vss vdd vdde2 data0 data2 data3 data4 data6 oe emios0 emios1 1234567891011
pinout and signal description spc564a74l7, spc564a80b4, spc564a80l7 39/157 doc id 15399 rev 9 figure 6. 324-pin pbga package ballmap (northeast, viewed from above) 12 13 14 15 16 17 18 19 20 21 22 an27 an28 an35 vssa1 an12_ sds mdo11_ etpua29_o mdo10_ etpua27_o mdo8_ etpua21_o vdd vrc33 vss a an26 an31 an32 vssa1 an13_ sdo mdo9_ etpua25_o mdo7_ etpua19_o mdo4_ etpua2_o mdo0 vss nic (1),(2) b an25 an30 an33 vdda1 an14_ sdi mdo5_ etpua4_o mdo2 mdo1 vss nic (1),(2) vdd c an24 an29 an34 vddeh7 an15_ fck mdo6_ etpua13_o mdo3 vss nic (1),(2) tck tdi d nic (1),(2) tms tdo nic (1) e nic (1),(2) jcomp evti evto f rdy mcko mseo0 mseo1 g vddeh6ab gpio203 gpio204 dspi_b_ sin h vss vss nic (1),(2) dspi_b_ sout dspi_b_ pcs3 dspi_b_ pcs0 dspi_b_ pcs1 j vss vss vss gpio99 dspi_b_ pcs4 dspi_b_ sck dspi_b_ pcs2 k vss vss vss dspi_b_ pcs5 dspi_a_ sout dspi_a_ sin dspi_a_ sck l 1. pins marked ?nic? hav e no internal connection. 2. balls b22, c21, d20, e19, f19 and j 14 are shorted together inside the package.
spc564a74l7, spc564a80b4, spc564a80l7 pinout and signal description doc id 15399 rev 9 40/157 figure 7. 324-pin pbga package ballmap (southeast, viewed from above) vss vss vss dspi_a_ pcs1 dspi_a_ pcs0 gpio98 vddreg m vss vss vss dspi_a_ pcs4 sci_a_tx dspi_a_ pcs5 nic (1) n vss vss vss can_c_tx sci_a_rx rstout rstcfg p wkpcfg can_c_rx sci_b_tx reset r sci_b_rx bootcfg1 vss (2) vss t vddeh6ab pllcfg1 bootcfg0 extal u vdd vrcctl pllref xtal v emios2 emios8 vddeh4ab emios12 emios21 vdde5 sci_c_tx vss vdd nic (1) vddpll w emios6 emios10 emios15 emios17 emios22 can_a_tx vdde5 sci_c_rx vss vdd vrc33 y emios5 emios9 emios13 emios16 emios19 emios23 can_a_rx vdde5 clkout vss vdd aa emios4 emios7 emios11 emios14 emios18 emios20 can_b_tx can_b_rx vdde5 engclk vss ab 12 13 14 15 16 17 18 19 20 21 22 1. pins marked ?nic? hav e no internal connection. 2. this pin (t21) should be tied low.
pinout and signal description spc564a74l7, spc564a80b4, spc564a80l7 41/157 doc id 15399 rev 9 2.4 signal summary table 4. spc564a80 signal properties name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltag e (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324 gpio emios14 (8) gpio[203] emios channel gpio p g 01 00 203 o i/o vddeh7 slow ? / up ? / up ? ? h20 emios15 (8) gpio[204] emios channel gpio p g 01 00 204 o i/o vddeh7 slow ? / up ?/ up ? ? h21 gpio[206] etrig0 gpio / eqadc trigger input g 00 206 i/o (9) vddeh7 slow (10) ? / up ? / up 143 r4 aa7 gpio[207] etrig1 gpio / eqadc trigger input g 00 207 i/o (9) vddeh7 slow ? / up ? / up 144 p5 y9 gpio[219] gpio g ? 219 (11) i/o vddeh7 multiv (12) ? / up ? / up 122 t6 ? reset / configuration reset external reset input p ? ? i vddeh6 slow reset / up reset / up 97 l16 r22 rstout external reset output p 01 230 o vddeh6 slow rstout / down rstout / down 102 k15 p21 pllref irq [4] etrig2 gpio[208] fmpll mode selection external interrupt request eqadc trigger input gpio p a1 a2 g 001 010 100 000 208 i i i i/o vddeh6 slow ? / up pllref / up 83 m14 v21 pllcfg1 (13) irq [5] dspi_d_sout gpio[209] ? external interrupt request dspi d data output gpio ? a1 a2 g ? 010 100 000 209 ? i o i/o vddeh6 medium ? / up ? / up ? ? u20 rstcfg gpio[210] rstcfg gpio p g 01 00 210 i i/o vddeh6 slow ? / down ???p22
spc564a74l7, spc564a80b4, spc564a80l7 pinout and signal description doc id 15399 rev 9 42/157 bootcfg[0] irq [2] gpio[211] boot config. input external interrupt request gpio p a1 g 01 10 00 211 i i i/o vddeh6 slow ? / down bootcfg[0] / down ??u21 bootcfg[1] irq [3] etrig3 gpio[212] boot config. input external interrupt request eqadc trigger input gpio p a1 a2 g 001 010 100 000 212 i i i i/o vddeh6 slow ? / down bootcfg[1] / down 85 m15 t20 wkpcfg nmi dspi_b_sout gpio[213] weak pull config. input non-maskable interrupt dspi d data output gpio p a1 a2 g 001 010 100 000 213 i i o i/o vddeh6 medium ? / up wkpcfg / up 86 l15 r19 external bus interface cs [0] addr[8] gpio[0] external chip selects external address bus gpio p a1 g 01 10 00 0 o i/o i/o vdde2 fast ? / up ? / up ? ? m4 cs [1] addr9 gpio[1] external chip selects external address bus gpio p a1 g 01 10 00 1 o i/o i/o vdde2 fast ? / up ? / up ? ? m3 cs [2] addr10 we[ 2]/be [2] cal_we [2]/be [2] gpio[2] external chip selects external address bus write/byte enable cal. bus write/byte enable gpio p a1 a2 a3 g 0001 0010 0100 1000 0000 2 o i/o o o i/o vdde2 fast ? / up ? / up ? ? n2 cs [3] addr11 we[ 3]/be [3] cal_we[ 3]/be [3] gpio[3] external chip selects external address bus write/byte enable cal bus write/byte enable gpio p a1 a2 a3 g 0001 0010 0100 1000 0000 3 o i/o o o i/o vdde2 fast ? / up ? / up ? ? n1 table 4. spc564a80 signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltag e (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324
pinout and signal description spc564a74l7, spc564a80b4, spc564a80l7 43/157 doc id 15399 rev 9 addr12 gpio[8] external address bus gpio p g 01 00 8 i/o i/o vdde3 fast ? / up ? / up ? ? t3 addr13 we[ 2] gpio[9] external address bus write/byte enable gpio p a2 g 001 100 000 9 i/o o i/o vdde3 fast ? / up ? / up ? ? u3 addr14 we[ 3] gpio[10] external address bus write/byte enables gpio p a2 g 001 100 000 10 i/o o i/o vdde3 fast ? / up ? / up ? ? u4 addr15 gpio[11] external address bus gpio p g 01 00 11 i/o i/o vdde3 fast ? / up ? / up ? ? v3 addr16 fr_a_tx data16 gpio[12] external address bus flexray tx data channel a external data bus gpio p a1 a2 g 001 010 100 000 12 i/o o i/o i/o vdde-eh medium ? / up ? / up ? ? p1 addr17 fr_a_tx_en data17 gpio[13] external address bus flexray ch. a tx data enable external data bus gpio p a1 a2 g 001 010 100 000 13 i/o o i/o i/o vdde-eh medium ? / up ? / up ? ? p2 addr18 fr_a_rx data18 gpio[14] external address bus flexray rx data ch. a external data bus gpio p a1 a2 g 001 010 100 000 14 i/o i i/o i/o vdde-eh medium ? / up ? / up ? ? r1 addr19 fr_b_tx data19 gpio[15] external address bus flexray tx data ch. b external data bus gpio p a1 a2 g 001 010 100 000 15 i/o o i/o i/o vdde-eh medium ? / up ? / up ? ? r2 addr20 fr_b_tx_en data20 gpio[16] external address bus flexray tx data enable for ch. b external data bus gpio p a1 a2 g 001 010 100 000 16 i/o o i/o i/o vdde-eh medium ? / up ? / up ? ? t1 table 4. spc564a80 signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltag e (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324
spc564a74l7, spc564a80b4, spc564a80l7 pinout and signal description doc id 15399 rev 9 44/157 addr21 fr_b_rx data21 gpio[17] external address bus flexray rx data channel b external data bus gpio p a1 a2 g 001 010 100 000 17 i/o i i/o i/o vdde-eh medium ? / up ? / up ? ? t2 addr22 data22 gpio[18] external address bus external data bus gpio p a2 g 001 100 000 18 i/o i/o i/o vdde-eh medium ? / up ? / up ? ? u1 addr23 data23 gpio[19] external address bus external data bus gpio p a2 g 001 100 000 19 i/o i/o i/o vdde-eh medium ? / up ? / up ? ? u2 addr24 data24 gpio[20] external address bus external data bus gpio p a2 g 001 100 000 20 i/o i/o i/o vdde-eh medium ? / up ? / up ? ? v1 addr25 data25 gpio[21] external address bus external data bus gpio p a2 g 001 100 000 21 i/o i/o i/o vdde-eh medium ? / up ? / up ? ? v2 addr26 data26 gpio[22] external address bus external data bus gpio p a2 g 001 100 000 22 i/o i/o i/o vdde-eh medium ? / up ? / up ? ? w1 addr27 data27 gpio[23] external address bus external data bus gpio p a2 g 001 100 000 23 i/o i/o i/o vdde-eh medium ? / up ? / up ? ? y2 addr28 data28 gpio[24] external address bus external data bus gpio p a2 g 001 100 000 24 i/o i/o i/o vdde-eh medium ? / up ? / up ? ? y1 addr29 data29 gpio[25] external address bus external data bus gpio p a2 g 001 100 000 25 i/o i/o i/o vdde-eh medium ? / up ? / up ? ? aa1 table 4. spc564a80 signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltag e (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324
pinout and signal description spc564a74l7, spc564a80b4, spc564a80l7 45/157 doc id 15399 rev 9 addr30 addr6 (8) data30 gpio[26] external address bus external address bus external data bus gpio p a1 a2 g 001 010 100 000 26 i/o o i/o i/o vdde-eh medium ? / up ? / up ? ? w3 addr31 addr7 (8) data31 gpio[27] external address bus external address bus external data bus gpio p a1 a2 g 001 010 100 000 27 i/o o i/o i/o vdde-eh medium ? / up ? / up ? ? v4 data0 addr16 gpio[28] external data bus external address bus gpio p a1 g 001 010 000 28 i/o i/o i/o vdde5 fast ? / up ? / up ? ? ab4 data1 addr17 gpio[29] external data bus external address bus gpio p a1 g 001 010 000 29 i/o i/o i/o vdde5 fast ? / up ? / up ? ? aa5 data2 addr18 gpio[30] external data bus external address bus gpio p a1 g 001 010 000 30 i/o i/o i/o vdde5 fast ? / up ? / up ? ? ab5 data3 addr19 gpio[31] external data bus external address bus gpio p a1 g 001 010 000 31 i/o i/o i/o vdde5 fast ? / up ? / up ? ? ab6 data4 addr20 gpio[32] external data bus external address bus gpio p a1 g 001 010 000 32 i/o i/o i/o vdde5 fast ? / up ? / up ? ? ab7 data5 addr21 gpio[33] external data bus external address bus gpio p a1 g 001 010 000 33 i/o i/o i/o vdde5 fast ? / up ? / up ? ? aa8 data6 addr22 gpio[34] external data bus external address bus gpio p a1 g 001 010 000 34 i/o i/o i/o vdde5 fast ? / up ? / up ? ? ab8 table 4. spc564a80 signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltag e (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324
spc564a74l7, spc564a80b4, spc564a80l7 pinout and signal description doc id 15399 rev 9 46/157 data7 addr23 gpio[35] external data bus external address bus gpio p a1 g 001 010 000 35 i/o i/o i/o vdde5 fast ? / up ? / up ? ? aa9 data8 addr24 gpio[36] external data bus external address bus gpio p a1 g 001 010 000 36 i/o i/o i/o vdde5 fast ? / up ? / up ? ? y6 data9 addr25 gpio[37] external data bus external address bus gpio p a1 g 001 010 000 37 i/o i/o i/o vdde5 fast ? / up ? / up ? ? y7 data10 addr26 gpio[38] external data bus external address bus gpio p a1 g 001 010 000 38 i/o i/o i/o vdde5 fast ? / up ? / up ? ? y8 data11 addr27 gpio[39] external data bus external address bus gpio p a1 g 001 010 000 39 i/o i/o i/o vdde5 fast ? / up ? / up ? ? w9 data12 addr28 gpio[40] external data bus external address bus gpio p a1 g 001 010 000 40 i/o i/o i/o vdde5 fast ? / up ? / up ? ? w10 data13 addr29 gpio[41] external data bus external address bus gpio p a1 g 001 010 000 41 i/o i/o i/o vdde5 fast ? / up ? / up ? ? y10 data14 addr30 gpio[42] external data bus external address bus gpio p a1 g 001 010 000 42 i/o i/o i/o vdde5 fast ? / up ? / up ? ? w11 data15 addr31 gpio[43] external data bus external address bus gpio p a1 g 001 010 000 43 i/o i/o i/o vdde5 fast ? / up ? / up ? ? y11 rd_wr gpio[62] external read/write gpio p g 01 00 62 i/o i/o vdde2 fast ? / up ? / up ? ? p3 table 4. spc564a80 signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltag e (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324
pinout and signal description spc564a74l7, spc564a80b4, spc564a80l7 47/157 doc id 15399 rev 9 bdip gpio[63] external burst data in progress gpio p g 01 00 63 o i/o vdde2 fast ? / up ? / up ? ? m1 we [0]/be [0] gpio[64] external write/byte enable gpio p g 01 00 64 o i/o vdde2 fast ? / up ? / up ? ? n4 we [1]/be [1] gpio[65] external write/byte enable gpio p g 01 00 65 o i/o vdde2 fast ? / up ? / up ? ? n3 oe gpio[68] external output enable gpio p g 01 00 68 o i/o vdde2 fast ? / up ? / up ? ? ab9 ts ale gpio[69] external transfer start address latch enable gpio[69] p a1 g 001 010 000 69 i/o o i/o vdde2 fast ? / up ? / up ? ? t4 ta ts (8) gpio[70] external transfer acknowledge external transfer start gpio p a1 g 001 010 000 70 i/o o i/o vdde2 fast ? / up ? / up ? ? r4 calibration bus cal_cs0 calibration chip select p 01 336 o vdde12 fast ?/? ? ? ? cal_cs2 cal_addr[10] cal_we [2]/be [2] calibration chip select calibration address bus calibration write/byte enable p a a2 001 010 100 338 o i/o o vdde12 fast ?/? ? ? ? cal_cs3 cal_addr[11] cal_we[ 3]/be [3] calibration chip select calibration address bus calibration write/byte enable p a a2 001 010 100 339 o i/o o vdde12 fast ?/? ? ? ? cal_addr[12] cal_we[ 2]/be [2] calibration address bus calibration write/byte enable p a 01 10 340 i/o o vdde12 fast ?/? ? ? ? cal_addr[13] cal_we[ 3]/be [3] calibration address bus calibration write/byte enable p a 01 10 340 i/o o vdde12 fast ?/? ? ? ? table 4. spc564a80 signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltag e (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324
spc564a74l7, spc564a80b4, spc564a80l7 pinout and signal description doc id 15399 rev 9 48/157 cal_addr[14] cal_data[31] calibration address bus calibration data bus p a 01 10 340 i/o i/o vdde12 fast ?/? ? ? ? cal_addr[15] cal_ale calibration address bus calibration address latch enable p a1 01 10 340 i/o o vdde12 fast ?/? ? ? ? cal_addr[16] cal_data[16] calibration address bus calibration data bus p a 01 10 345 i/o i/o vdde12 fast ?/? ? ? ? cal_addr[17] cal_data[17] calibration address bus calibration data bus p a 01 10 345 i/o i/o vdde12 fast ?/? ? ? ? cal_addr[18] cal_data[18] calibration address bus calibration data bus p a 01 10 345 i/o i/o vdde12 fast ?/? ? ? ? cal_addr[19] cal_data[19] calibration address bus calibration data bus p a 01 10 345 i/o i/o vdde12 fast ?/? ? ? ? cal_addr[20] cal_data[20] calibration address bus calibration data bus p a 01 10 345 i/o i/o vdde12 fast ?/? ? ? ? cal_addr[21] cal_data[21] calibration address bus calibration data bus p a 01 10 345 i/o i/o vdde12 fast ?/? ? ? ? cal_addr[22] cal_data[22] calibration address bus calibration data bus p a 01 10 345 i/o i/o vdde12 fast ?/? ? ? ? cal_addr[23] cal_data[23] calibration address bus calibration data bus p a 01 10 345 i/o i/o vdde12 fast ?/? ? ? ? cal_addr[24] cal_data[24] calibration address bus calibration data bus p a 01 10 345 i/o i/o vdde12 fast ?/? ? ? ? cal_addr[25] cal_data[25] calibration address bus calibration data bus p a 01 10 345 i/o i/o vdde12 fast ?/? ? ? ? cal_addr[26] cal_data[26] calibration address bus calibration data bus p a 01 10 345 i/o i/o vdde12 fast ?/? ? ? ? cal_addr[27] cal_data[27] calibration address bus calibration data bus p a 01 10 345 i/o i/o vdde12 fast ?/? ? ? ? table 4. spc564a80 signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltag e (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324
pinout and signal description spc564a74l7, spc564a80b4, spc564a80l7 49/157 doc id 15399 rev 9 cal_addr[28] cal_data[28] calibration address bus calibration data bus p a 01 10 345 i/o i/o vdde12 fast ?/? ? ? ? cal_addr[29] cal_data[29] calibration address bus calibration data bus p a 01 10 345 i/o i/o vdde12 fast ?/? ? ? ? cal_addr[30] cal_data[30] calibration address bus calibration data bus p a 01 10 345 i/o i/o vdde12 fast ?/? ? ? ? cal_data[0] calibration data bus p 01 341 i/o vdde12 fast ? / up ? / up ? ? ? cal_data[1] calibration data bus p 01 341 i/o vdde12 fast ? / up ? / up ? ? ? cal_data[2] calibration data bus p 01 341 i/o vdde12 fast ? / up ? / up ? ? ? cal_data[3] calibration data bus p 01 341 i/o vdde12 fast ? / up ? / up ? ? ? cal_data[4] calibration data bus p 01 341 i/o vdde12 fast ? / up ? / up ? ? ? cal_data[5] calibration data bus p 01 341 i/o vdde12 fast ? / up ? / up ? ? ? cal_data[6] calibration data bus p 01 341 i/o vdde12 fast ? / up ? / up ? ? ? cal_data[7] calibration data bus p 01 341 i/o vdde12 fast ? / up ? / up ? ? ? cal_data[8] calibration data bus p 01 341 i/o vdde12 fast ? / up ? / up ? ? ? cal_data[9] calibration data bus p 01 341 i/o vdde12 fast ? / up ? / up ? ? ? cal_data[10] calibration data bus p 01 341 i/o vdde12 fast ? / up ? / up ? ? ? table 4. spc564a80 signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltag e (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324
spc564a74l7, spc564a80b4, spc564a80l7 pinout and signal description doc id 15399 rev 9 50/157 cal_data[11] calibration data bus p 01 341 i/o vdde12 fast ? / up ? / up ? ? ? cal_data[12] calibration data bus p 01 341 i/o vdde12 fast ? / up ? / up ? ? ? cal_data[13] calibration data bus p 01 341 i/o vdde12 fast ? / up ? / up ? ? ? cal_data[14] calibration data bus p 01 341 i/o vdde12 fast ? / up ? / up ? ? ? cal_data[15] calibration data bus p 01 341 i/o vdde12 fast ? / up ? / up ? ? ? cal_rd_wr calibration read/write enable p 01 342 o vdde12 fast ?/? ? ? ? cal_we [0]/be [0] calibration write/byte enable p 01 342 o vdde12 fast ?/? ? ? ? cal_we[ 1]/be [1] calibration write/byte enable p 01 342 o vdde12 fast ?/? ? ? ? cal_oe calibration output enable p 01 342 o vdde12 fast ?/? ? ? ? cal_ts cal_ale calibration transfer start address latch enable p a 01 10 343 o o vdde12 fast ?/? ? ? ? cal_mdo[4] calibration nexus message data out p01 ? o vdde12 fast ? cal_mdo[4] / ? ? ? ? cal_mdo[5] calibration nexus message data out p01 ? o vdde12 fast ? cal_mdo[5] / ? ? ? ? cal_mdo[6] calibration nexus message data out p01 ? o vdde12 fast ? cal_mdo[6] / ? ? ? ? cal_mdo[7] calibration nexus message data out p01 ? o vdde12 fast ? cal_mdo[7] / ? ? ? ? table 4. spc564a80 signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltag e (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324
pinout and signal description spc564a74l7, spc564a80b4, spc564a80l7 51/157 doc id 15399 rev 9 cal_mdo[8] calibration nexus message data out p01 ? o vdde12 fast ? cal_mdo[8] / ? ? ? ? cal_mdo[9] calibration nexus message data out p01 ? o vdde12 fast ? cal_mdo[9] / ? ? ? ? cal_mdo[10] calibration nexus message data out p01 ? o vdde12 fast ? cal_mdo[10] / ? ? ? ? cal_mdo[11] calibration nexus message data out p01 ? o vdde12 fast ? cal_mdo[11] / ? ? ? ? nexus evti nexus event in p 01 231 i vddeh7 multiv (12),(14) ? / up evti / up 116 e15 f21 evto nexus event out p 01 227 o vddeh7 multiv (12),(14), (15) ? evto / ? 120 d15 f22 mcko nexus message clock out p ? 219 (11 ) o vrc33 fast ? mcko / ? 14 f15 g20 mdo0 (16) nexus message data out p 01 220 o vrc33 fast ? mdo[0] / ? 17 a14 b20 mdo1 (16) nexus message data out p 01 221 o vrc33 fast ? mdo[1] / ? 18 b14 c19 mdo2 (16) nexus message data out p 01 222 o vrc33 fast ? mdo[2] / ? 19 a13 c18 mdo3 (16) nexus message data out p 01 223 o vrc33 fast ? mdo[3] / ? 20 b13 d18 mdo4 (16) etpua2_o (8) gpio[75] nexus message data out etpu a channel (output only) gpio p a1 g 01 10 00 75 o o i/o vddeh7 multiv (12),(14) ? ? / ? 126 p10 b19 table 4. spc564a80 signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltag e (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324
spc564a74l7, spc564a80b4, spc564a80l7 pinout and signal description doc id 15399 rev 9 52/157 mdo5 (16) etpua4_o (8) gpio[76] nexus message data out etpu a channel (output only) gpio p a1 g 01 10 00 76 o o i/o vddeh7 multiv (12),(14) ? ? / ? 129 t10 c17 mdo6 (16) etpua13_o (8) gpio[77] nexus message data out etpu a channel (output only) gpio p a1 g 01 10 00 77 o o i/o vddeh7 multiv (12),(14) ? ? / ? 135 t11 d17 mdo7 (16) etpua19_o (8) gpio[78] nexus message data out etpu a channel (output only) gpio p a1 g 01 10 00 78 o o i/o vddeh7 multiv (12),(14) ? ? / ? 136 n11 b18 mdo8 (16) etpua21_o (8) gpio[79] nexus message data out etpu a channel (output only) gpio p a1 g 01 10 00 79 o o i/o vddeh7 multiv (12),(14) ? ? / ? 137 p11 a19 mdo9 (16) etpua25_o (8) gpio[80] nexus message data out etpu a channel (output only) gpio p a1 g 01 10 00 80 o o i/o vddeh7 multiv (12),(14) ? ? / ? 139 t7 b17 mdo10 (16) etpua27_o (8) gpio[81] nexus message data out etpu a channel (output only) gpio p a1 g 01 10 00 81 o o i/o vddeh7 multiv (12),(14) ? ? / ? 134 r10 a18 mdo11 (16) etpua29_o (8) gpio[82] nexus message data out etpu a channel (output only) gpio[82] p a1 g 01 10 00 82 o o i/o vddeh7 multiv (12),(14) ? ? / ? 124 p9 a17 mseo [0] (16) nexus message start/end out p 01 224 o vddeh7 multiv (12),(14) ? mseo[0] / ? 118 c15 g21 mseo [1] (16) nexus message start/end out p 01 225 o vddeh7 multiv (12),(14) ? mseo[1] / ? 117 e16 g22 rdy nexus ready output p 01 226 o vddeh7 multiv (12),(14) ????g19 jtag table 4. spc564a80 signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltag e (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324
pinout and signal description spc564a74l7, spc564a80b4, spc564a80l7 53/157 doc id 15399 rev 9 tck jtag test clock input p 01 ? i vddeh7 multiv (12) tck / down tck / down 128 c16 d21 tdi jtag test data input p 01 232 i vddeh7 multiv (12) tdi / up tdi / up 130 e14 d22 tdo jtag test data output p 01 228 o vddeh7 multiv (12) tdo / up tdo / up 123 f14 e21 tms jtag test mode select input p 01 ? i vddeh7 multiv (12) tms / up tms / up 131 d14 e20 jcomp jtag tap controller enable p 01 ? i vddeh7 multiv (12) jcomp / down jcomp / down 121 f16 f20 flexcan can_a_tx sci_a_tx gpio[83] flexcan a tx esci a tx gpio p a1 g 01 10 00 83 o o i/o vddeh6 slow ? / up ? / up 81 p12 y17 can_a_rx sci_a_rx gpio[84] flexcan a rx esci a rx gpio p a1 g 01 10 00 84 i i i/o vddeh6 slow ? / up ? / up 82 r12 aa18 can_b_tx dspi_c_pcs[3] sci_c_tx gpio[85] flexcan b tx dspi c peripheral chip select esci c tx gpio p a1 a2 g 001 010 100 000 85 o o o i/o vddeh6 slow ? / up ? / up 88 t12 ab18 can_b_rx dspi_c_pcs[4] sci_c_rx gpio[86] flexcan b rx dspi c peripheral chip select esci c rx gpio p a1 a2 g 001 010 100 000 86 i o i i/o vddeh6 slow ? / up ? / up 89 r13 ab19 can_c_tx dspi_d_pcs[3] gpio[87] flexcan c tx dspi d peripheral chip select gpio p a1 g 01 10 00 87 o o i/o vddeh6 medium ? / up ? / up 101 k13 p19 table 4. spc564a80 signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltag e (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324
spc564a74l7, spc564a80b4, spc564a80l7 pinout and signal description doc id 15399 rev 9 54/157 can_c_rx dspi_d_pcs[4] gpio[88] flexcan c rx dspi d peripheral chip select gpio p a1 g 01 10 00 88 i o i/o vddeh6 slow ? / up ? / up 98 l14 r20 esci sci_a_tx emios13 (8) gpio[89] esci a tx emios channel gpio p a1 g 01 10 00 89 o o i/o vddeh6 medium ? / up ? / up 100 j14 n20 sci_a_rx emios15 (8) gpio[90] esci a rx emios channel gpio p a1 g 01 10 00 90 i o i/o vddeh6 medium ? / up ? / up 99 k14 p20 sci_b_tx dspi_d_pcs[1] gpio[91] esci b tx dspi d peripheral chip select gpio p a1 g 01 10 00 91 o o i/o vddeh6 medium ? / up ? / up 87 l13 r21 sci_b_rx dspi_d_pcs[5] gpio[92] esci b rx dspi d peripheral chip select gpio p a1 g 01 10 00 92 i o i/o vddeh6 medium ? / up ? / up 84 m13 t19 sci_c_tx gpio[244] esci c tx gpio p g 01 00 244 o i/o vddeh6 medium ? / up ? / up ? ? w18 sci_c_rx gpio[245] esci c rx gpio p g 01 00 245 i i/o vddeh6 medium ? / up ? / up ? ? y19 dspi dspi_a_sck (17) dspi_c_pcs[1] gpio[93] ? dspi c peripheral chip select gpio ? a1 g ? 10 00 93 ? o i/o vddeh7 medium ? / up ? / up ? ? l22 dspi_a_sin (17) dspi_c_pcs[2] gpio[94] ? dspi c peripheral chip select gpio ? a1 g ? 10 00 94 ? o i/o vddeh7 medium ? / up ? / up ? ? l21 table 4. spc564a80 signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltag e (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324
pinout and signal description spc564a74l7, spc564a80b4, spc564a80l7 55/157 doc id 15399 rev 9 dspi_a_sout (17) dspi_c_pcs[5] gpio[95] ? dspi c peripheral chip select gpio ? a1 g ? 10 00 95 ? o i/o vddeh7 medium ? / up ? / up ? ? l20 dspi_a_pcs[0] (17) dspi_d_pcs[2] gpio[96] ? dspi d peripheral chip select gpio ? a1 g ? 10 00 96 ? o i/o vddeh7 medium ? / up ? / up ? ? m20 dspi_a_pcs[1] (17) dspi_b_pcs[2] gpio[97] ? dspi b peripheral chip select gpio ? a1 g ? 10 00 97 ? o i/o vddeh7 medium ? / up ? / up ? ? m19 cs[2] dspi_d_sck gpio[98] ? spi clock pin for dspi module gpio ? a1 g ? 10 00 98 ? i/o i/o vddeh7 medium ? / up ? / up 141 j15 m21 cs[3] dspi_d_sin gpio[99] ? dspi d data input gpio ? a1 g ? 10 00 99 ? i i/o vddeh7 medium ? / up ? / up 142 h13 k19 dspi_a_pcs[4] (17) dspi_d_sout gpio[100] ? dspi d data output gpio ? a1 g ? 10 00 100 o i/o vddeh7 medium ? / up ? / up ? ? n19 dspi_a_pcs[5] (17) dspi_b_pcs[3] gpio[101] ? dspi b peripheral chip select gpio ? a1 g ? 10 00 101 o i/o vddeh7 medium ? / up ? / up ? ? n21 dspi_b_sck dspi_c_pcs[1] gpio[102] spi clock pin for dspi module dspi c peripheral chip select gpio p a1 g 01 10 00 102 i/o o i/o vddeh6 medium ? / up ? / up 106 j16 k21 dspi_b_sin dspi_c_pcs[2] gpio[103] dspi b data input dspi c peripheral chip select gpio p a1 g 01 10 00 103 i o i/o vddeh6 medium ? / up ? / up 112 g15 h22 table 4. spc564a80 signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltag e (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324
spc564a74l7, spc564a80b4, spc564a80l7 pinout and signal description doc id 15399 rev 9 56/157 dspi_b_sout dspi_c_pcs[5] gpio[104] dspi b data output dspi c peripheral chip select gpio p a1 g 01 10 00 104 o o i/o vddeh6 medium ? / up ? / up 113 g13 j19 dspi_b_pcs[0] dspi_d_pcs[2] gpio[105] dspi b peripheral chip select dspi d peripheral chip select gpio p a1 g 01 10 00 105 i/o o i/o vddeh6 medium ? / up ? / up 111 g16 j21 dspi_b_pcs[1] dspi_d_pcs[0] gpio[106] dspi b peripheral chip select dspi d peripheral chip select gpio p a1 g 01 10 00 106 o i/o i/o vddeh6 medium ? / up ? / up 109 h16 j22 dspi_b_pcs[2] dspi_c_sout gpio[107] dspi b peripheral chip select dspi c data output gpio p a1 g 01 10 00 107 o o i/o vddeh6 medium ? / up ? / up 107 h15 k22 dspi_b_pcs[3] dspi_c_sin gpio[108] dspi b peripheral chip select dspi c data input gpio p a1 g 01 10 00 108 o i i/o vddeh6 medium ? / up ? / up 114 g14 j20 dspi_b_pcs[4] dspi_c_sck gpio[109] dspi b peripheral chip select spi clock pin for dspi module gpio p a1 g 01 10 00 109 o i/o i/o vddeh6 medium ? / up ? / up 105 h14 k20 dspi_b_pcs[5] dspi_c_pcs[0] gpio[110] dspi b peripheral chip select dspi c peripheral chip select gpio p a1 g 01 10 00 110 o i/o i/o vddeh6 medium ? / up ? / up 104 j13 l19 eqadc an0 (18) dan0+ single ended analog input positive terminal diff. input p? ? i i vdda analog i / ? an[0] / ? 172 b5 b8 an1 (18) dan0- single ended analog input negative terminal diff. input p? ? i i vdda analog i / ? an[1] / ? 171 a6 a8 an2 (18) dan1+ single ended analog input positive terminal diff. input p? ? i i vdda analog i / ? an[2] / ? 170 d6 d10 table 4. spc564a80 signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltag e (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324
pinout and signal description spc564a74l7, spc564a80b4, spc564a80l7 57/157 doc id 15399 rev 9 an3 (18) dan1- single ended analog input negative terminal diff. input p? ? i i vdda analog i / ? an[3] / ? 169 c7 c9 an4 (18) dan2+ single ended analog input positive terminal diff. input p? ? i i vdda analog i / ? an[4] / ? 168 b6 b9 an5 (18) dan2- single ended analog input negative terminal diff. input p? ? i i vdda analog i / ? an[5] / ? 167 a7 a9 an6 (18) dan3+ single ended analog input positive terminal diff. input p? ? i i vdda analog i / ? an[6] / ? 166 d7 d11 an7 (18) dan3- single ended analog input negative terminal diff. input p? ? i i vdda analog i / ? an[7] / ? 165 c8 c10 an8 anw single-ended analog input multiplexed analog input p01 ? i vdda analog i / ? an[8] / ? 9 b3 d6 an9 anx single-ended analog input external multiplexed analog input p01 ? i i vdda analog i / ? an[9] / ? 5 a2 d7 an10 any single-ended analog input multiplexed analog input p01 ? i vdda analog i / ? an[10] / ? ? ? d8 an11 anz single-ended analog input multiplexed analog input p01 ? i vdda analog i / ? an[11] / ? 4 a3 a5 an12 - sds ma0 etpua19_o (8) sds single-ended analog input mux address 0 etpu a channel (output only) eqadc serial data select p a1 a2 g 001 010 100 000 215 i o o i/o vddeh7 (19) medium i / ? an[12] / ? 148 a12 a16 an13 - sdo ma1 etpua21_o (8) sdo single-ended analog input mux address 1 etpu a channel (output only) eqadc serial data out p a1 a2 g 001 010 100 000 216 i o o o vddeh7 (19) medium i / ? an[13] / ? 147 b12 b16 table 4. spc564a80 signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltag e (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324
spc564a74l7, spc564a80b4, spc564a80l7 pinout and signal description doc id 15399 rev 9 58/157 an14 - sdi ma2 etpua27_o (8) sdi single-ended analog input mux address 2 etpu a channel (output only) eqadc serial data in p a1 a2 g 001 010 100 000 217 i o o i vddeh7 (19) medium i / ? an[14] / ? 146 c12 c16 an15 - fck fck etpua29_o (8) single-ended analog input eqadc free running clock etpu a channel (output only) p a1 a2 001 010 100 218 i o o vddeh7 (19) medium i / ? an[15] / ? 145 c13 d16 an16 single-ended analog input p ? ? i vdda analog i / ? an[16] / ? 3 c6 b7 an17 single-ended analog input p ? ? i vdda analog i / ? an[17] / ? 2 c4 c6 an18 single-ended analog input p ? ? i vdda analog i / ? an[18] / ? 1 d5 d9 an19 single-ended analog input p ? ? i vdda analog i / ? an[19] / ? ? ? b6 an20 single-ended analog input p ? ? i vdda analog i / ? an[20] / ? ? ? c7 an21 single-ended analog input p ? ? i vdda analog i / ? an[21] / ? 173 b4 c8 an22 single-ended analog input p ? ? i vdda analog i / ? an[22] / ? 161 b8 c11 an23 single-ended analog input p ? ? i vdda analog i / ? an[23] / ? 160 c9 b11 an24 single-ended analog input p ? ? i vdda analog i / ? an[24] / ? 159 d8 d12 an25 single-ended analog input p ? ? i vdda analog i / ? an[25] / ? 158 b9 c12 table 4. spc564a80 signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltag e (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324
pinout and signal description spc564a74l7, spc564a80b4, spc564a80l7 59/157 doc id 15399 rev 9 an26 single-ended analog input p ? ? i vdda analog i / ? an[26] / ? ? ? b12 an27 single-ended analog input p ? ? i vdda analog i / ? an[27] / ? 157 a10 a12 an28 single-ended analog input p ? ? i vdda analog i / ? an[28] / ? 156 b10 a13 an29 single-ended analog input p ? ? i vdda analog i / ? an[29] / ? ? ? d13 an30 single-ended analog input p ? ? i vdda analog i / ? an[30] / ? 155 d9 c13 an31 single-ended analog input p ? ? i vdda analog i / ? an[31] / ? 154 d10 b13 an32 single-ended analog input p ? ? i vdda analog i / ? an[32] / ? 153 c10 b14 an33 single-ended analog input p ? ? i vdda analog i / ? an[33] / ? 152 c11 c14 an34 single-ended analog input p ? ? i vdda analog i / ? an[34] / ? 151 c5 d14 an35 single-ended analog input p ? ? i vdda analog i / ? an[35] / ? 150 d11 a14 an36 single-ended analog input p ? ? i vdda analog i / ? an[36] / ? 174 f4 b4 an37 single-ended analog input p ? ? i vdda analog i / ? an[37] / ? 175 e3 a4 an38 single-ended analog input p ? ? i vdda analog i / ? an[38] / ? ? ? c5 an39 single-ended analog input p ? ? i vdda analog i / ? an[39] / ? 8 d2 b5 table 4. spc564a80 signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltag e (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324
spc564a74l7, spc564a80b4, spc564a80l7 pinout and signal description doc id 15399 rev 9 60/157 vrh voltage reference high p ? ? i vdda ? i / ? vrh 163 a8 a10 vrl voltage reference low p ? ? i vdda ? i / ? vrl 162 a9 a11 refbybc reference bypass capacitor input p? ? i vdda analog i / ? refbypc 164 b7 b10 etpu2 tcrclka irq [7] gpio[113] etpu a tcr clock external interrupt request gpio p a1 g 01 10 00 113 i i i/o vddeh4 slow ? / up ? / up ? l4 m2 etpua0 etpua12_o (8) etpua19_o (8) gpio[114] etpu a channel etpu a channel (output only) etpu a channel (output only) gpio p a1 a2 g 001 010 100 000 114 i/o o o i/o vddeh4 slow ? / wkpcfg ? / wkpcfg 61 n3 l3 etpua1 etpua13_o (8) gpio[115] etpu a channel etpu a channel (output only) gpio p a1 g 01 10 00 115 i/o o i/o vddeh4 slow ? / wkpcfg ? / wkpcfg 60 m3 l4 etpua2 etpua14_o (8) gpio[116] etpu a channel etpu a channel (output only) gpio p a1 g 01 10 00 116 i/o o i/o vddeh4 slow ? / wkpcfg ? / wkpcfg 59 p2 k3 etpua3 etpua15_o (8) gpio[117] etpu a channel etpu a channel (output only) gpio p a1 g 01 10 00 117 i/o o i/o vddeh4 slow ? / wkpcfg gpio / wkpcfg 58 p1 l2 etpua4 etpua16_o (8) fr_b_tx gpio[118] etpu a channel etpu a channel (output only) flexray tx data channel b gpio p a1 a3 g 0001 0010 1000 0000 118 i/o o o i/o vddeh4 slow ? / wkpcfg ? / wkpcfg 56 n2 l1 table 4. spc564a80 signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltag e (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324
pinout and signal description spc564a74l7, spc564a80b4, spc564a80l7 61/157 doc id 15399 rev 9 etpua5 etpua17_o (8) dspi_b_sck_lvd s- fr_b_tx_en gpio[119] etpu a channel etpu a channel (output only) lvds negative dspi clock flexray tx data enable for ch. b gpio p a1 a2 a3 g 0001 0010 0100 1000 0000 119 i/o o o o i/o vddeh4 slow + lvd s ? / wkpcfg ? / wkpcfg 54 m4 k4 etpua6 etpua18_o (8) dspi_b_sck_lvd s+ fr_b_rx gpio[120] etpu a channel etpu a channel (output only) lvds positive dspi clock flexray rx data channel b gpio p a1 a2 a3 g 0001 0010 0100 1000 0000 120 i/o o o i i/o vddeh4 medium + lvd s ? / wkpcfg ? / wkpcfg 53 l3 j3 etpua7 etpua19_o (8) dspi_b_sout_lv ds- etpua6_o (8) gpio[121] etpu a channel etpu a channel (output only) lvds negative dspi data out etpu a channel (output only) gpio p a1 a2 a3 g 0001 0010 0100 1000 0000 121 i/o o o o i/o vddeh4 slow + lvd s ? / wkpcfg ? / wkpcfg 52 k3 k2 etpua8 etpua20_o (8) dspi_b_sout_lv ds+ gpio[122] etpu a channel etpu a channel (output only) lvds positive dspi data out gpio p a1 a2 g 001 010 100 000 122 i/o o o i/o vddeh4 slow + lvd s ? / wkpcfg ? / wkpcfg 51 n1 k1 etpua9 etpua21_o (8) rch1_b gpio[123] etpu a channel etpu a channel (output only) reaction channel 1b gpio p a1 a2 g 001 010 100 000 123 i/o o o i/o vddeh4 slow ? / wkpcfg ? / wkpcfg 50 m2 j4 etpua10 etpua22_o (8) rch1_c gpio[124] etpu a channel etpu a channel (output only) reaction channel 1c gpio p a1 a2 g 001 010 100 000 124 i/o o o i/o vddeh1 slow ? / wkpcfg ? / wkpcfg 49 m1 h3 table 4. spc564a80 signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltag e (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324
spc564a74l7, spc564a80b4, spc564a80l7 pinout and signal description doc id 15399 rev 9 62/157 etpua11 etpua23_o (8) rch4_b gpio[125] etpu a channel etpu a channel (output only) reaction channel 4b gpio p a1 a2 g 001 010 100 000 125 i/o o o i/o vddeh1 slow ? / wkpcfg ? / wkpcfg 48 l2 j2 etpua12 dspi_b_pcs[1] rch4_c gpio[126] etpu a channel dspi b peripheral chip select reaction channel 4c gpio p a1 a2 g 001 010 100 000 126 i/o o o i/o vddeh1 medium ? / wkpcfg ? / wkpcfg 47 l1 j1 etpua13 dspi_b_pcs[3] gpio[127] etpu a channel dspi b peripheral chip select gpio p a1 g 01 10 00 127 i/o o i/o vddeh1 medium ? / wkpcfg ? / wkpcfg 46 j4 g4 etpua14 dspi_b_pcs[4] etpua9_o (8) rch0_a gpio[128] etpu a channel dspi b peripheral chip select etpu a channel (output only) reaction channel 0a gpio p a1 a2 a3 g 0001 0010 0100 1000 0000 128 i/o o o o i/o vddeh1 medium ? / wkpcfg ? / wkpcfg 42 j3 g3 etpua15 dspi_b_pcs[5] rch1_a gpio[129] etpu a channel dspi b peripheral chip select reaction channel 1a gpio p a1 a2 g 001 010 100 000 129 i/o o o i/o vddeh1 medium ? / wkpcfg ? / wkpcfg 40 k2 h2 etpua16 dspi_d_pcs[1] rch2_a gpio[130] etpu a channel dspi d peripheral chip select reaction channel 2a gpio p a1 a2 g 001 010 100 000 130 i/o o o i/o vddeh1 slow ? / wkpcfg ? / wkpcfg 39 k1 h1 etpua17 dspi_d_pcs[2] rch3_a gpio[131] etpu a channel dspi d peripheral chip select reaction channel 3a gpio p a1 a2 g 001 010 100 000 131 i/o o o i/o vddeh1 slow ? / wkpcfg ? / wkpcfg 38 h3 f3 table 4. spc564a80 signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltag e (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324
pinout and signal description spc564a74l7, spc564a80b4, spc564a80l7 63/157 doc id 15399 rev 9 etpua18 dspi_d_pcs[3] rch4_a gpio[132] etpu a channel dspi d peripheral chip select reaction channel 4a gpio p a1 a2 g 001 010 100 000 132 i/o o o i/o vddeh1 slow ? / wkpcfg ? / wkpcfg 37 h4 f4 etpua19 dspi_d_pcs[4] rch5_a gpio[133] etpu a channel dspi d peripheral chip select reaction channel 5a gpio p a1 a2 g 001 010 100 000 133 i/o o o i/o vddeh1 slow ? / wkpcfg ? / wkpcfg 36 j2 g2 etpua20 irq [8] rch0_b fr_a_tx gpio[134] etpu a channel external interrupt request reaction channel 0b flexray tx data channel a gpio p a1 a2 a3 g 0001 0010 0100 1000 0000 134 i/o i o o i/o vddeh1 slow ? / wkpcfg ? / wkpcfg 35 j1 g1 etpua21 irq [9] rch0_c fr_a_rx gpio[135] etpu a channel external interrupt request reaction channel 0c flexray rx channel a gpio p a1 a2 a3 g 0001 0010 0100 1000 0000 135 i/o i o i i/o vddeh1 slow ? / wkpcfg ? / wkpcfg 34 g4 e4 etpua22 irq [10] etpua17_o (8) gpio[136] etpu a channel external interrupt request etpu a channel (output only) gpio p a1 a2 g 001 010 100 000 136 i/o i o i/o vddeh1 slow ? / wkpcfg ? / wkpcfg 32 h2 f2 etpua23 irq [11] etpua21_o (8) fr_a_tx_en gpio[137] etpu a channel external interrupt request etpu a channel (output only) flexray ch. a tx enable gpio p a1 a2 a3 g 0001 0010 0100 1000 0000 137 i/o i o o i/o vddeh1 slow ? / wkpcfg ? / wkpcfg 30 h1 f1 table 4. spc564a80 signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltag e (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324
spc564a74l7, spc564a80b4, spc564a80l7 pinout and signal description doc id 15399 rev 9 64/157 etpua24 irq [12] dspi_c_sck_lvd s- gpio[138] etpu a channel external interrupt request lvds negative dspi clock gpio p a1 a2 g 001 010 100 000 138 i/o i o i/o vddeh1 slow + lvd s ? / wkpcfg ? / wkpcfg 28 g1 e1 etpua25 irq [13] dspi_c_sck_lvd s+ gpio[139] etpu a channel external interrupt request lvds positive dspi clock gpio p a1 a2 g 001 010 100 000 139 i/o i o i/o vddeh1 medium + lvd s ? / wkpcfg ? / wkpcfg 27 g3 e3 etpua26 irq [14] dspi_c_sout_lv ds- gpio[140] etpu a channel external interrupt request lvds negative dspi data out gpio p a1 a2 g 001 010 100 000 140 i/o i o i/o vddeh1 slow + lvd s ? / wkpcfg ? / wkpcfg 26 f3 d3 etpua27 irq [15] dspi_c_sout_lv ds+ dspi_b_sout gpio[141] etpu a channel external interrupt request lvds positive dspi data out dspi data out gpio p a1 a2 a3 g 0001 0010 0100 1000 0000 141 i/o i o o i/o vddeh1 slow + lvd s ? / wkpcfg ? / wkpcfg 25 g2 e2 etpua28 dspi_c_pcs[1] rch5_b gpio[142] etpu a channel dspi c peripheral chip select reaction channel 5b gpio p a1 a2 g 001 010 100 000 142 i/o o o i/o vddeh1 medium ? / wkpcfg ? / wkpcfg 24 f1 d1 etpua29 dspi_c_pcs[2] rch5_c gpio[143] etpu a channel dspi c peripheral chip select reaction channel 5c gpio p a1 a2 g 001 010 100 000 143 i/o o o i/o vddeh1 medium ? / wkpcfg ? / wkpcfg 23 f2 d2 table 4. spc564a80 signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltag e (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324
pinout and signal description spc564a74l7, spc564a80b4, spc564a80l7 65/157 doc id 15399 rev 9 etpua30 dspi_c_pcs[3] etpua11_o (8) gpio[144] etpu a channel dspi c peripheral chip select etpu a channel (output only) gpio p a1 a2 g 001 010 100 000 144 i/o o o i/o vddeh1 medium ? / wkpcfg ? / wkpcfg 22 e1 c1 etpua31 dspi_c_pcs[4] etpua13_o (8) gpio[145] etpu a channel dspi c peripheral chip select etpu a channel (output only) gpio p a1 a2 g 001 010 100 000 145 i/o o o i/o vddeh1 medium ? / wkpcfg ? / wkpcfg 21 e2 c2 emios emios0 etpua0_o (8) etpua25_o (8) gpio[179] emios channel etpu a channel (output only) etpu a channel (output only) gpio p a1 a2 g 001 010 100 000 179 i/o o o i/o vddeh4 slow ? / up ? / up 63 t4 ab10 emios1 etpua1_o (8) gpio[180] emios channel etpu a channel (output only) gpio p a1 g 01 10 00 180 i/o o i/o vddeh4 slow ? / up ? / up 64 t5 ab11 emios2 etpua2_o (8) rch2_b gpio[181] emios channel etpu a channel (output only) reaction channel 2b gpio p a1 a2 g 001 010 100 000 181 i/o o o i/o vddeh4 slow ? / up ? / up 65 n7 w12 emios3 etpua3_o (8) gpio[182] emios channel etpu a channel (output only) gpio p a1 g 01 10 00 182 i/o o i/o vddeh4 slow ? / wkpcfg ? / wkpcfg 66 r6 aa11 emios4 etpua4_o (8) rch2_c gpio[183] emios channel etpu a channel (output only) reaction channel 2c gpio p a1 a2 g 001 010 100 000 183 i/o o o i/o vddeh4 slow ? / wkpcfg ? / wkpcfg 67 r5 ab12 table 4. spc564a80 signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltag e (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324
spc564a74l7, spc564a80b4, spc564a80l7 pinout and signal description doc id 15399 rev 9 66/157 emios5 etpua5_o (8) gpio[184] emios channel etpu a channel (output only) gpio p a1 g 01 10 00 184 i/o o i/o vddeh4 slow ? / wkpcfg ? / wkpcfg ? ? aa12 emios6 etpua6_o (8) gpio[185] emios channel etpu a channel (output only) gpio p a1 g 01 10 00 185 i/o o i/o vddeh4 slow ? / down ? / down 68 p7 y12 emios7 etpua7_o (8) gpio[186] emios channel etpu a channel (output only) gpio p a1 g 01 10 00 186 i/o o i/o vddeh4 slow ? / down ? / down 69 ? ab13 emios8 etpua8_o (8) sci_b_tx gpio[187] emios channel etpu a channel (output only) esci b tx gpio p a1 a2 g 001 010 100 000 187 i/o o o i/o vddeh4 slow ? / up ? / up 70 p8 w13 emios9 etpua9_o (8) sci_b_rx gpio[188] emios channel etpu a channel (output only) esci b rx gpio p a1 a2 g 001 010 100 000 188 i/o o i i/o vddeh4 slow ? / up ? / up 71 r7 aa13 emios10 dspi_d_pcs[3] rch3_b gpio[189] emios channel dspi d peripheral chip select reaction channel 3b gpio p a1 a2 g 001 010 100 000 189 i/o o o i/o vddeh4 medium ? / wkpcfg ? / wkpcfg 73 n8 y13 emios11 dspi_d_pcs[4] rch3_c gpio[190] emios channel dspi d peripheral chip select reaction channel 3c gpio p a1 a2 g 001 010 100 000 190 i/o o o i/o vddeh4 medium ? / wkpcfg ? / wkpcfg 75 r8 ab14 emios12 dspi_c_sout etpua27_o (8) gpio[191] emios channel dspi c data output etpu a channel (output only) gpio p a1 a2 g 001 010 100 000 191 i/o o o i/o vddeh4 medium ? / wkpcfg ? / wkpcfg 76 n10 w15 table 4. spc564a80 signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltag e (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324
pinout and signal description spc564a74l7, spc564a80b4, spc564a80l7 67/157 doc id 15399 rev 9 emios13 dspi_d_sout gpio[192] emios channel dspi d data output gpio p a1 g 01 10 00 192 i/o o i/o vddeh4 medium ? / wkpcfg ? / wkpcfg 77 t8 aa14 emios14 irq [0] etpua29_o (8) gpio[193] emios channel external interrupt request etpu a channel (output only) gpio p a1 a2 g 001 010 100 000 193 i/o i o i/o vddeh4 slow ? / down ? / down 78 r9 ab15 emios15 irq [1] gpio[194] emios channel external interrupt request gpio p a1 g 01 10 00 194 i/o i i/o vddeh4 slow ? / down ? / down 79 t9 y14 emios16 gpio[195] emios channel gpio p g 01 00 195 i/o i/o vddeh4 slow ? / up ? / up ? ? aa15 emios17 gpio[196] emios channel gpio p g 01 00 196 i/o i/o vddeh4 slow ? / up ? / up ? ? y15 emios18 gpio[197] emios channel gpio p g 01 00 197 i/o i/o vddeh4 slow ? / up ? / up ? ? ab16 emios19 gpio[198] emios channel gpio p g 01 00 198 i/o i/o vddeh4 slow ? / wkpcfg ? / wkpcfg ? ? aa16 emios20 gpio[199] emios channel gpio p g 01 00 199 i/o i/o vddeh4 slow ? / wkpcfg ? / wkpcfg ? ? ab17 emios21 gpio[200] emios channel gpio p g 01 00 200 i/o i/o vddeh4 slow ? / wkpcfg ? / wkpcfg ??w16 emios22 gpio[201] emios channel gpio p g 01 00 201 i/o i/o vddeh4 slow ? / down ? / down ? ? y16 emios23 gpio[202] emios channel gpio p g 01 00 202 i/o i/o vddeh4 slow ? / down ? / down 80 r11 aa17 clock synthesizer table 4. spc564a80 signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltag e (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324
spc564a74l7, spc564a80b4, spc564a80l7 pinout and signal description doc id 15399 rev 9 68/157 xtal crystal oscillator output p 01 ? o vddeh6 analog ??93p16v22 extal extclk crystal oscillator input external clock input p a 01 10 ?i vddeh6 analog ??92n16u22 clkout system clock output p 01 229 o vdde5 fast ? clkout ? ? aa20 engclk engineering clock output p 01 214 o vdde5 fast ? engclk ? t14 ab21 power / ground vddreg voltage regulator supply ? ? i 5 v i / ? vddreg 10 k16 m22 vrcctl voltage regulator control output ? ? o ? o / ? vrcctl 11 n14 v20 vrc33 (20) internal regulator output ? ? o 3.3 v i/o / ? vrc33 13 a15, d1, n6, n12 a21, b1, p4, w7, y22 input for external 3.3 v supply ? ? 3.3 v vdda eqadc high reference voltage ? ? i 5 v i / ? vdda 6 ? ? vssa eqadc ground/low reference voltage ? ? i ? i / ? vssa 7 ? ? vdda0 (21) eqadc high reference voltage ? ? i 5 v i / ? vdda0 ? b11 a6 vssa0 (22) eqadc ground/low reference voltage ? ? i ? i / ? vssa0 ? a11 a7 vdda1 (21) eqadc high reference voltage ? ? i 5 v i / ? vdda1 ? a4 c15 vssa1 (22) eqadc ground/low reference voltage ? ? i ? i / ? vssa1 ? a5 a15, b15 vddpll fmpll supply voltage ? ? i 1.2 i / ? vddpll 91 r16 w22 vstby power supply for standby ram ? ? i 0.9 v - 6 v i / ? vstby 12 c1 a3 table 4. spc564a80 signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltag e (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324
pinout and signal description spc564a74l7, spc564a80b4, spc564a80l7 69/157 doc id 15399 rev 9 vdd core supply for input or decoupling ? ? i 1.2 v i / ? vdd 33, 45, 62, 103, 132, 149, 176 b1, b16, c2, d3, e4, n5, p4, p13, r3, r14, t2, t15 a2, a20, b3, c4, c22, d5, v19, w5, w20, y4, y21, aa3, aa22, ab2 vdde12 external supply input for calibration bus interfaces ? ? i 1.8 v - 3.3 v i / ? vdde12 ? ? ? vdde2 (23) external supply input for ebi interfaces ? ? i 1.8 v - 3.3 v i / ? vdde2 (24) ?? m9, m10, n11, p11, w6, w8, y5, aa4, aa6, aa10, ab3 vdde5 external supply input for engclk, clkout and ebi signals data[0:15] ? ? i 1.8 v - 3.3 v i / ? vdde5 ? t13 w17, y18, aa19, ab20 vdde-eh external supply for ebi interfaces ? ? i 3.0 v - 5 v i / ? vdde-eh ? ? r3, w2 vddeh1a (25) i/o supply input ? ? i 3.3 v - 5.0 v i / ? vddeh1a (25) 31 ? ? vddeh1b (25) i/o supply input ? ? i 3.3 v - 5.0 v i / ? vddeh1b (25) 41 ? ? vddeh1ab (25) i/o supply input ? ? i 3.3 v - 5.0 v i / ? vddeh1ab (25) ?k4 h4 vddeh4 (26) i/o supply input ? ? i 3.3 v - 5.0 v i / ? vddeh4 (26) ?? ? vddeh4a (26) i/o supply input ? ? i 3.3 v - 5.0 v i / ? vddeh4a (26) 55 ? ? vddeh4b (26) i/o supply input ? ? i 3.3 v - 5.0 v i / ? vddeh4b (26) 74 ? ? table 4. spc564a80 signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltag e (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324
spc564a74l7, spc564a80b4, spc564a80l7 pinout and signal description doc id 15399 rev 9 70/157 vddeh4ab (26) i/o supply input ? ? i 3.3 v - 5.0 v i / ? vddeh4ab (26) ?n9 w14 vddeh6 (27) i/o supply input ? ? i 3.3 v - 5.0 v i / ? vddeh6 (27) ?? ? vddeh6a (27) i/o supply input ? ? i 3.3 v - 5.0 v i / ? vddeh6a (27) 95 ? ? vddeh6b (27) i/o supply input ? ? i 3.3 v - 5.0 v i / ? vddeh6b (27) 110 ? ? vddeh6ab (27) i/o supply input ? ? i 3.3 v - 5.0 v i / ? vddeh6ab (27) ? f13 h19, u19 vddeh7 i/o supply input ? ? i 3.3 v - 5.0 v i / ? vddeh7 ? d12 d15 vddeh7a i/o supply input ? ? i 3.3 v - 5.0 v i / ? vddeh7a 125 ? ? table 4. spc564a80 signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltag e (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324
pinout and signal description spc564a74l7, spc564a80b4, spc564a80l7 71/157 doc id 15399 rev 9 vddeh7b i/o supply input ? ? i 3.3 v - 5.0 v i / ? vddeh7b 138 ? ? vss ground ? ? i ? i / ? vss 15, 29, 43, 57, 72, 90, 94, 96, 108, 115, 127, 133, 140 a1, a16, b2, b15, c3, c14, d4, d13, g7, g8, g9, g10, h7, h8, h9, h10, j7, j8, j9, j10, k7, k8, k9, k10, m16, n4, n13, p3, p14, r2, r15, t1, t16 a1, a22, b2, b21, c3, c20, d4, d19, j9, j10, j11, j12, j13, k9, k10, k11, k12, k13, k14, l9, l10, l11, l12, l13, l14, m11, m12, m13, m14, n9, n10, n12, n13, n14, p9, p10, p12, p13, p14, t21, t22, w4,w19, y3, y20, aa2, aa21, ab1, ab22 1. for each pin in the table, each line in the function column is a separate function of the pin. for all i/o pins the selection of primary pin function or secondary function or gpio is done in the siu except where explicitly noted. s ee the signal details table for a description of each signal. 2. the p/a/g column indicates the position a signal occupies in t he muxing order for a pin?primary, alternate 1, alternate 2, al ternate 3, or gpio. signals are selected by setting the pa field value in the appropriate pcr register in t he siu module. the pa field values are as follows: p - 0b0001, a 1 - 0b0010, a2 - 0b0100, a3 - 0b1000, or g - 0b0000. depending on the register, the pa field si ze can vary in length. for pa fields having fewer than four bits, remove the appropriate number of leading zeroes from these values. 3. the pad configuration register (pcr) pa fiel d is used by software to select pin function. 4. values in the pcr no. column refer to registers in the system integration unit (siu). the actu al register name is ?siu_pcr? s uffixed by the pcr number. for example, pcr[190] refers to the siu register named siu_pcr190. 5. the vdde and vddeh supply inputs are broken into segments. each segment of slow i/o pins (vdd eh) may have a separate supply i n the 3.3 v to 5.0 v range (- 10%/+5%). each segment of fast i/o (vdde) may have a separate supply in the 1.8 v to 3.3 v range (+/- 10%). 6. see table 5 for details on pad types. table 4. spc564a80 signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltag e (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324
spc564a74l7, spc564a80b4, spc564a80l7 pinout and signal description doc id 15399 rev 9 72/157 7. the status during reset pin is sampled after the internal po r is negated. prior to exiting po r, the signal has a high impedan ce. terminology is o - output, i - input, up - weak pull up enabled, down - weak pull down enabled, low - output driven low, high - output driven high. a dash for the functio n in this column denotes that both the input and output buffer are turned off. the signal name to the left or right of the slash indi cates the pin is enabled. 8. output only. 9. when used as etrig, this pin must be c onfigured as an input. for gpio it can be configured either as an input or output. 10. maximum frequency is 50 khz. 11. the siu_pcr219 register is unus ual in that it controls pads for two separat e device pins: gpio[219] and mcko. see the spc564 a80 microcontrolle r reference manual (siu chapter) for details. 12. multivoltage pads are automatically configured in low swing mode when a jtag or nexus function is selected, otherwise they a re high swing. 13. on lqfp176 and lbga208 packages, th is pin is tied low internally. 14. nexus multivoltage pads default to 5 v operation until the nexus module is enabled. 15. evto should be clamped to 3.3 v to prevent possible damage to external tools that only support 3.3 v. 16. do not connect pin directly to a power supply or ground. 17. this signal name is used to support legacy naming. 18. during and just after por negates, internal pull resistors can be enabled, resulting in as much as 4 ma of current draw. the pull resistors are disabled when the system clock propagates through the device. 19. for pins an12-an15, if the analog features are used the vddeh7 input pins should be tied to v dda because that segment must m eet the vdda specification to support analog input function. 20. do not use vrc33 to drive external circuits. 21. vdda0 and vdda1 are shorted together internally in bga packages. in the qfp package the two pads are double bonded on one pi n called vdda. 22. vssa0 and vssa1 are shorted together internally in bga pack ages. in the qfp package the two pads are double bonded on one pi n called vssa. 23. vdde2 and vdde3 are shorted together in all production packages. 24. vdde2 and vdde3 are shorted together in all production packages. 25. vddeh1a, vddeh1b, and vddeh1ab are shorted together in all production packages. the separation of the signal names is presen t to support legacy naming, however they should be considered as th e same signal in this document. 26. vddeh4, vddeh4a, vddeh4b, and vddeh4ab are shorted together in all production pack ages. the separation of the signal names i s present to support legacy naming, however they should be considered as the same signal in this document. 27. vddeh6, vddeh6a, vddeh6b, and vddeh6ab are shorted together in all production pack ages. the separation of the signal names i s present to support legacy naming, however they should be considered as the same signal in this document.
spc564a74l7, spc564a80b4, spc564a80l7 pinout and signal description doc id 15399 rev 9 73/157 2.5 signal details table 5. pad types pad type name i/o voltage range slow pad_ssr_hv 3.0v - 5.5 v medium pad_msr_hv 3.0 v - 5.5 v fast pad_fc 3.0 v - 3.6 v multiv (1),(2) 1. multivoltage pads are automatically configured in low swing mode when a jtag or nexus function is selected, otherwise they are high swing. 2. vddeh7 supply cannot be below 4.5 v when in low-swing mode. pad_multv_hv 3.0 v - 5.5 v (high swing mode) 3.0 v - 3.6 v (low swing mode) analog pad_ae_hv 0.0 - 5.5 v lvds pad_lo_lv ? table 6. signal details signal module or function description clkout clock generation spc564a80 clock output for the external/calibration bus interface engclk clock generation clock for external asic devices extal clock generation input pin for an external crystal oscillator or an external clock source based on the value driven on the pllref pin at reset. pllref clock generation reset/configuration pllref is used to select whether the oscillator operates in xtal mode or external reference mode from reset. pllref=0 selects external reference mode. on the 324bga package, pllref is bonded to the ball used for pllcfg[0] for compatibility with previous devices . for the 176-pin qfp and 208-ball bga packages: 0: external reference clock is selected. 1: xtal oscillator mode is selected for the 324 ball bga package: if rstcfg is 0: 0: external reference clock is selected. 1: xtal oscillator mode is selected. if rstcfg is 1, xtal oscillator mode is selected. xtal clock generation crystal oscillator input dspi_b_sck_lvds- dspi_b_sck_lvds+ dspi lvds pair used for dspi_b tsb mode transmission dspi_b_sout_lvds- dspi_b_sout_lvds+ dspi lvds pair used for dspi_b tsb mode transmission
pinout and signal description spc 564a74l7, spc564a80b4, spc564a80l7 74/157 doc id 15399 rev 9 dspi_c_sck_lvds- dspi_c_sck_lvds+ dspi lvds pair used for dspi_c tsb mode transmission dspi_c_sout_lvds- dspi_c_sout_lvds+ dspi lvds pair used for dspi_c tsb mode transmission pcs_b[0] pcs_c[0] pcs_d[0] dspi_b - dspi_d peripheral chip select when device is in master mode?slave select when used in slave mode pcs_b[1:5] pcs_c[1:5] pcs_d[1:5] dspi_b - dspi_d peripheral chip select when device is in master mode?not used in slave mode sck_b sck_c sck_d dspi_b - dspi_d dspi clock?output when device is in master mode; input when in slave mode sin_b sin_c sin_d dspi_b - dspi_d dspi data in sout_b sout_c sout_d dspi_b - dspi_d dspi data out addr[10:31] ebi the addr[10:31] signals specify the physical address of the bus transaction. the 26 address lines correspond to bits 3-31 of the ebi?s 32-bit internal address bus. addr[15:31] can be used as address and data signals when configured appropriately for a multiplexed external bus. this allows 32-bit data operations, or 16-bit data operations without using data[0:15] signals. ale ebi the address latch enable (ale) signal is used to demultiplex the address from the data bus. it is asserted while the least significant 16 bits of the addres s are present in the multiplexed address/data bus. bdip ebi bdip is asserted to indicate t hat the master is requesting another data beat following the current one. cs [0:3] ebi cs x is asserted by the master to in dicate that this transaction is targeted for a particular memory bank on the primary external bus. data[0:31] ebi the data[0:31] signals contain the data to be transferred for the current transaction. oe ebi oe is used to indicate when an external memory is permitted to drive back read data. external memories must have their data output buffers off when oe is negated. oe is only asserted for chip-select accesses. table 6. signal details (continued) signal module or function description
spc564a74l7, spc564a80b4, spc564a80l7 pinout and signal description doc id 15399 rev 9 75/157 rd_wr ebi rd_wr indicates whether the current transaction is a read access or a write access. ta ebi ta is asserted to indicate that the slave has received the data (and completed the acce ss) for a write cycle, or returned data for a read cycle. if the transaction is a burst read, ta is asserted for each one of the transaction beats. for write transactions, ta is only asserted once at access completion, even if more than one write data beat is transferred. ts ebi the transfer start signal (ts ) is asserted by the spc564a80 to indicate the start of a transfer. we [2:3] ebi write enables are used to enable program operations to a particular memory. we [2:3] are only asserted for write accesses we [0:3]/be [0:3] ebi write enables are used to enable program operations to a particular memory. these signals can also be used as byte enables for read and write operation by setting the webs bit in the appropriate ebi base register (ebi_br n ). we [0:3] are only asserted for write accesses. be [0:3] are asserted for both read and write accesses emios[0:23] emios emios i/o channels an[0:39] eqadc single-ended analog inputs for analog-to-digital converter fck eqadc eqadc free running clock for eqadc ssi. ma[0:2] eqadc these three control bits are output to enable the selection for an external analog mux for expansion channels. refbypc eqadc bypass capacitor input sdi eqadc serial data in sdo eqadc serial data out sds eqadc serial data select vrh eqadc voltage reference high input vrl eqadc voltage reference low input sci_a_rx sci_b_rx sci_c_rx esci_a - esci_c esci receive sci_a_tx sci_b_tx sci_c_tx esci_a - esci_c esci transmit etpu_a[0:31] etpu etpu i/o channel table 6. signal details (continued) signal module or function description
pinout and signal description spc 564a74l7, spc564a80b4, spc564a80l7 76/157 doc id 15399 rev 9 rch0_[a:c] rch1_[a:c] rch2_[a:c] rch3_[a:c] rch4_[a:c] rch5_[a:c] etpu2 reaction module etpu2 reaction channels. used to control external actuators, e.g., solenoid control for dire ct injection systems and valve control in automatic transmissions tcrclka etpu2 input clock for tcr time base can_a_tx can_b_tx can_c_tx flexcan_a - flexcan_c flexcan transmit can_a_rx can_b_rx can_c_rx flexcan_a - flexcan_c flexcan receive fr_a_rx fr_b_rx flexray flexray receive (channels a, b) fr_a_tx_en fr_b_tx_en flexray flexray transmit enable (channels a, b) fr_a_tx fr_b_tx flexray flexray transmit (channels a, b) jcomp jtag enables the jtag tap controller. tck jtag clock input for the on-chip test logic. tdi jtag serial test instruction and data input for the on-chip test logic. tdo jtag serial test data output for the on-chip test logic. tms jtag controls test mode operations for the on-chip test logic. evti nexus evti is an input that is read on the negation of reset to enable or disable the nexus debug port. after reset, the evti pin is used to initiate program synchronization messages or generate a breakpoint. evto nexus output that provides timing to a development tool for a single watchpoint or breakpoint occurrence. mcko nexus mcko is a free running clock output to the development tools which is used for timing of the mdo and mseo signals. mdo[0:11] (1) nexus trace message output to development tools. this pin also indicates the status of the cryst al oscillator clock following a power-on reset, when mdo[0] is driven high until the crystal oscillator clock achieves stability and is then negated. mseo [0:1] (1) nexus output pin?indicates the start or end of the variable length message on the mdo pins rdy nexus nexus ready output (rdy ) is an output that indicates to the development tools the data is ready to be read from or written to the nexus read/write access registers. table 6. signal details (continued) signal module or function description
spc564a74l7, spc564a80b4, spc564a80l7 pinout and signal description doc id 15399 rev 9 77/157 bootcfg[0:1] siu - configuration two bootcfg signals are implemented in spc564a80 mcus. the bam program uses the bootcfg0 bit to determine where to read the reset config uration word, and whether to initiate a flexcan or esci boot. the bootcfg1 pin is sampled during the assertion of the rstout signal, and the value is used to update the rsr and the bam boot mode see the spc564a80 microcontroller reference manual for more information. the following values are for bootcfg[0:1}: 00:boot from internal flash memory 01:flexcan/esci boot 10:boot from external memory using ebi 11:reserved note: for the 176-pin qfp and 208-ball bga packages bootcfg[0] is always 0 sinc e the ebi interface is not available. wkpcfg siu - configuration the wkpcfg pin is applied at the assertion of the internal reset signal (assertion of rstout ), and is sampled 4 clock cycles before the negation of the rstout pin. the value is used to config ure whether the etpu and emios pins are connected to internal weak pull up or weak pull down devices after reset. the value latched on the wkpcfg pin at reset is stored in the reset status register (rsr), and is updated for all reset sources except the debug port reset and software external reset. 0:weak pulldown applied to etpu and emios pins at reset 1:weak pullup applied to etpu and emios pins at reset. etrig[2:3] siu - eqadc triggers external signal etrigx triggers eqadc cfifox gpio[206] etrig0 (input) siu - eqadc triggers external signal etrigx triggers eqadc cfifox gpio[207] etrig1 (input) siu - eqadc triggers external signal etrigx triggers eqadc cfifox table 6. signal details (continued) signal module or function description
pinout and signal description spc 564a74l7, spc564a80b4, spc564a80l7 78/157 doc id 15399 rev 9 irq [0:5] irq [7:15] siu - external interrupts the irq [0:15] pins connect to the siu irq inputs. imux select register 1 is used to select the irq [0:15] pins as inputs to the irqs. see the spc564a80 microcontroller reference manual for more information. nmi siu - external interrupts non-maskable interrupt gpio[0:3] gpio[8:43] gpio[62:65] gpio[68:70] gpio[75:145] gpio[179:204] gpio[208:213] gpio[219] gpio[244:245] siu - gpio configurable general purpose i/o pins. each gpio input and output is separately controlled by an 8-bit input (gpdi) or output (gpdo) register. additionally, each gpio pins is configured using a dedicated siu_pcr register. the gpio pins are generally multiplexed with other i/o pin functions. see the spc564a80 microcontroller reference manual for more information. ? reset siu - reset the reset pin is an active low input. the reset pin is asserted by an external device during a power-on or external reset. the internal reset sign al asserts only if the reset pin asserts for 10 clock cycles. assertion of the reset pin while the device is in reset causes the reset cycle to start over. the reset pin has a glitch detector which detects spikes greater than two clock cycles in duration that fall below the switch point of the input buffer logic of the vddeh input pins. the switch point lies between the maximum vil and minimum vih specifications for the vddeh input pins. rstcfg siu - reset used to enable or disable the pllref and the bootcfg[0:1] configuration signals. 0:get configuration informat ion from bootcfg[0:1] and pllref 1:use default configuration of booting from internal flash with crystal clock source for the 176-pin qfp and 208-ball bga packages rstcfg is always 0, so pllref and bootcfg signals are used. rstout siu - reset the rstout pin is an active low output that uses a push/pull configuration. the rstout pin is driven to the low state by the mcu for all internal and external reset sources. there is a delay between initiation of the reset and the assertion of the rstout pin. 1. do not connect pin directly to a power supply or ground. table 6. signal details (continued) signal module or function description
spc564a74l7, spc564a80b4, spc564a80l7 pinout and signal description doc id 15399 rev 9 79/157 table 7. power/ground segmentation power segment voltage i/o pins powered by segment vdde2 1.8 v - 3.3 v cs0, cs 1, cs2, cs3,rd_wr, bdip, we0, we1, oe, ts, ta vdde3 1.8 v - 3.3 v addr12, addr13, addr14, addr15 vdde5 1.8 v - 3.3 v data0, data1, data2, data3, data4, data5, data6, data7, data8, data9, data10, data11, data12, data13, data14, data15, clkout, engclk vdde12 1.8 v - 3.3 v cal_cs0, cal_cs2, cal_cs 3 cal_addr12, cal_addr13, cal_addr14, cal_addr15, cal_addr16, cal_addr17, cal_addr18, cal_addr19, cal_addr20, cal_addr21, cal_addr22, cal_addr23, cal_addr24, cal_addr25, cal_addr26, cal_addr27, cal_addr28, cal_addr29, cal_addr30, cal_data0, cal_data1, cal_data2, cal_data3, cal_data4, cal_data5, cal_data6, cal_data7, cal_data8, cal_data9, cal_data10, cal_data11, cal_data12, cal_data13, cal_data14, cal_data15, cal_rd_wr, cal_we0, cal_we1, cal_oe, cal_ts vdde-eh 3.0 v - 5 v addr16, addr17, addr18, addr19, addr20, addr21, addr22, addr23, addr24, addr25, addr26, addr27, addr28, addr29, addr30, addr31 vddeh1 3.3 v - 5.0 v etpua10, etpua11, etpua12, etpua13, etpua14, etpua15, etpua16, etpua17, etpua18, etpua19, etpua20, etpua21, etpua22, etpua23, etpua24, etpua25, etpua26, etpua27, etpua28, etpua29, etpua30, etpua31 vddeh4 3.3 v - 5.0 v emios0, emios1, emios2, emio s3, emios4, emios5, emios6, emios7, emios8, emios9, em ios10, emios11, emios12, emios13, emios14, emios15, emios16, emios17, emios18, emios19, emios20, emios21, emios22, emios23, tcrclka, etpua0, etpua1, etpua2, etpua3, etpua4, etpua5, etpua6, etpua7, etpua8, etpua9, etpua0 vddeh6 3.3 v - 5.0 v reset , rstout , pllref, pllcfg1, rstcfg, bootcfg0, bootcfg1, wkpcfg, can_a_tx, can_a_rx, can_b_tx, can_b_rx, can_c_tx, can_c_rx, sci_a_tx, sci_a_rx, sci_b_tx, sci_c_rx, dspi_b_sck, dspi_b_sin, dspi_b_sout, dspi_b_pcs[0], dspi_b_pcs[1], dspi_b_pcs[2], dspi_b_pcs[3], dspi_b_pcs[4], dspi_b_pcs[5], sci_b_rx, sci_c_tx, extal, xtal vddeh7 3.3 v - 5.0 v emios14, emios 15, gpio98, gpio99, gpio203, gpio204, gpio206, gpio207, gpio219, evti, evto, mdo4, mdo5, mdo6, mdo7, mdo8, md o9, mdo10, mdo11, mseo0, mseo1, rdy, tck, tdi, tdo, tms, jcomp, dspi_a_sck, dspi_a_sin, dspi_a_sout, dspi_a_pcs[0], dspi_a_pcs[1], dspi_a_pcs[4], dspi_a_pcs[5], an12-sds, an13-sdo, an14- sdi, an15-fck vdda 5 v an0, an1, an2, an3, an4, an5, an6, an7, an8, an9, an10, an11, an16, an17, an18, an19 , an20, an21, an22, an23, an24, an25, an26, an27, an28 , an29, an30, an31, an32, an33, an34, an35, an36, an37 , an38, an39, vrh, vrl, refbybc vrc33 (1) 3.3 v mcko, mdo0, mdo1, mdo2, mdo3
pinout and signal description spc 564a74l7, spc564a80b4, spc564a80l7 80/157 doc id 15399 rev 9 other power segments vddreg 5 v ? vrcctl ? ? vddpll 1.2 v ? vstby 0.95?1.2 v (unregulated mode) ? 2.0?5.5 v (regulated mode) ? vss ? ? 1. do not use vrc33 to drive external circuits. table 7. power/ground segmentation (continued) power segment voltage i/o pins powered by segment
spc564a74l7, spc564a80b4, spc564a80l7 electrical characteristics doc id 15399 rev 9 81/157 3 electrical characteristics this section contains detaile d information on power considerations, dc/ac electrical characteristics, and ac timing specifications for the spc564a80 series of mcus. the electrical specifications are prelimin ary and are from previous designs, design simulations, or initial evaluation. these specifications may not be fully tested or guaranteed at this early stage of the product life c ycle, however for production silicon these specifications will be met. finalized specif ications will be published after complete characterization and device qualifications have been completed. in the tables where the device logic provides signals with their respective timing characteristics, the symbol ?cc? for controller characteristics is included in the symbol column. in the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol ?sr? for system requirement is included in the symbol column. 3.1 parameter classification the electrical parameters shown in this supplement are guaranteed by various methods. to give the customer a better understanding, the classifications listed in ta b l e 8 are used and the parameters are tagged accordingly in the tables where appropriate. note: the classification is shown in the column labeled ?c? in the parameter tables where appropriate. table 8. parameter classifications classification tag tag description p those parameters are guaranteed during production testing on each individual device. c those parameters are achieved by the design c haracterization by measuring a statistically relevant sample size across process variations. t those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwi se noted. all values shown in the typical column are within this category. d those parameters are derived mainly from simulations.
electrical characteristics spc564a74l7, spc564a80b4, spc564a80l7 82/157 doc id 15399 rev 9 3.2 maximum ratings table 9. absolute maximum ratings (1) symbol parameter conditions value unit min max v dd sr 1.2 v core supply voltage (2) ?0.3 1.32 v v flash sr flash core voltage (3),(4) ?0.3 3.6 v v stby sr sram standby voltage (5) ?0.3 6 v v ddpll sr clock synthesizer voltage ?0.3 1.32 v v rc33 sr voltage regulator control input voltage (4) ?0.3 3.6 v v dda sr analog supply voltage (5) reference to v ssa ?0.3 5.5 v v dde sr i/o supply voltage (4),(6) ?0.3 3.6 v v ddeh sr i/o supply voltage (5) ?0.3 5.5 v v in sr dc input voltage (7) v ddeh powered i/o pads ?1.0 (8) v ddeh + 0.3 v (9) v v dde powered i/o pads ?1.0 (10) v dde + 0.3 v (10) v dda powered i/o pads ?1.0 5.5 v ddreg sr voltage regulator supply voltage ?0.3 5.5 v v rh sr analog reference high voltage reference to vrl ?0.3 5.5 v v ss ? v ssa sr v ss differential voltage ?0.1 0.1 v v rh ? v rl sr v ref differential voltage ?0.3 5.5 v v rl ? v ssa sr vrl to v ssa differential voltage ?0.3 0.3 v v sspll ? v ss sr v sspll to v ss differential voltage ?0.1 0.1 v i maxd sr maximum dc digital input current (11) per pin, applies to all digital pins ?3 3 ma i maxa sr maximum dc analog input current (12) per pin, applies to all analog pins ?5ma
spc564a74l7, spc564a80b4, spc564a80l7 electrical characteristics doc id 15399 rev 9 83/157 3.3 thermal characteristics t j sr maximum operating temperature range - die junction temperature ?40.0 150.0 o c t stg sr storage temperature range ?55.0 150.0 o c t sdr sr maximum solder temperature (13) ? 260.0 o c msl sr moisture sensitivity level (14) ?3 1. functional operating conditions ar e given in the dc electrical s pecifications. absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guarant eed. stress beyond the listed maxima may affect device reliability or cause permanent damage to the device. 2. allowed 2 v for 10 hours cumulative time, remaining time at 1.2 v +10%. 3. the v flash supply is connected to v rc33 in the package substrate. this specif ication applies to calibration package devices only. 4. allowed 5.3 v for 10 hours cumulative time, remaining time at 3.3 v +10%. 5. allowed 5.9 v for 10 hours cumulative time, remaining time at 5 v +10%. 6. all functional non-supply i/ o pins are clamped to v ss and v dde , or v ddeh . 7. ac signal overshoot and undershoot of up to 2.0 v of the i nput voltages is permitted for an accumulative duration of 60 hours over the complete lifetime of the device (i njection current not limi ted for this duration). 8. internal structures hold the volt age greater than ?1.0 v if the injection current limit of 2 ma is met. 9. internal structures hold the input voltage less than the maximum voltage on all pads powered by v ddeh supplies, if the maximum injection current specificat ion is met (2 ma for all pins) and v ddeh is within the operating voltage specifications. 10. internal structures hold the input voltage less than the maximum voltage on all pads powered by v dde supplies, if the maximum injection current specificat ion is met (2 ma for all pins) and v dde is within the operating voltage specifications. 11. total injection current for all pins (includi ng both digital and analog) must not exceed 25 ma. 12. total injection current for all anal og input pins must not exceed 15 ma. 13. solder profile per ipc/jedec j-std-020d. 14. moisture sensitivity per jedec test method a112. table 9. absolute maximum ratings (1) (continued) symbol parameter conditions value unit min max table 10. thermal characteristics for 176-pin qfp (1) symbol c parameter conditions value unit r ? ja cc d junction-to-ambient, natural convection (2) single layer board - 1s 38 c/w r ? ja cc d junction-to-ambient, natural convection (2) four layer board - 2s2p 31 c/w r ? jma cc d junction-to-moving-air, ambient (2) 200 ft./min., single layer board - 1s 30 c/w r ? jma cc d junction-to-moving-air, ambient (2) at 200 ft./min., four layer board - 2s2p 25 c/w r ? jb cc d junction-to-board (3) 20 c/w
electrical characteristics spc564a74l7, spc564a80b4, spc564a80l7 84/157 doc id 15399 rev 9 r ? jctop cc d junction-to-case (4) 5c/w ? jt cc d junction-to-package top, natural convection (5) 2c/w 1. thermal characteristics ar e targets based on simulation that are s ubject to change per devic e characterization. 2. junction-to-ambient thermal resist ance determined per jedec jesd51-3 and jesd51-6. thermal test board meets jedec specification for this package. 3. junction-to-board thermal re sistance determined per jedec jesd51-8. ther mal test board meets jedec specification for the specified package. 4. junction-to-case at the top of the package determined using mil-std 883 method 1012.1. the cold plate temperature is used for the case temperature. reported value incl udes the thermal resistance of the interface layer. 5. thermal characterization parameter indicating the tem perature difference between the package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the therma l characterization pa rameter is written as psi-jt. table 10. thermal characteristics for 176-pin qfp (1) (continued) symbol c parameter conditions value unit table 11. thermal characteristics for 208-pin lbga (1) symbol c parameter conditions value unit r ? ja cc d junction-to-ambient, natural convection (2),(3) one layer board - 1s 39 c/w r ? ja cc d junction-to-ambient, natural convection (2),(4) four layer board - 2s2p 24 c/w r ? jma cc d junction-to-moving-air, ambient (2),(4) at 200 ft./min., one layer board 31 c/w r ? jma cc d junction-to-moving-air, ambient (2),(4) at 200 ft./min., four layer board 2s2p 20 c/w r ? jb cc d junction-to-board (5) four layer board - 2s2p 13 c/w r ? jc cc d junction-to-case (6) 6c/w ? jt cc d junction-to-package top natural convection (7) 2c/w 1. thermal characteristics ar e targets based on simulation that are s ubject to change per devic e characterization. 2. junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power diss ipation of other components on the board, and board thermal resistance. 3. per semi g38-87 and jedec jesd51-2 wi th the single-layer board horizontal. 4. per jedec jesd51-6 wi th the board horizontal. 5. thermal resistance between the die and th e printed circuit board per jedec jesd51- 8. board temperature is measured on the top surface of the board near the package. 6. indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1) with the cold plate temperature used for the case temperature. 7. thermal characterization parameter indicating the te mperature difference between package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the therma l characterization pa rameter is written as psi-jt.
spc564a74l7, spc564a80b4, spc564a80l7 electrical characteristics doc id 15399 rev 9 85/157 3.3.1 general notes for s pecifications at maximu m junction temperature an estimation of the chip junction temperature, t j , can be obtained from the equation: equation 1 t j = t a + (r ? ja * p d ) where: t a = ambient temperature for the package ( o c) r ? ja = junction-to-ambient thermal resistance ( o c/w) p d = power dissipation in the package (w) the thermal resistance values used are based on the jedec jesd51 series of standards to provide consistent values for estimations and comparisons. the difference between the values determined for the single-layer (1s) board compared to a four-layer board that has two signal layers, a power and a ground plane (2s2p), demonstrate that the effective thermal resistance is not a constant. the thermal resistance depends on the: construction of the application board (number of planes) effective size of the board which cools the component quality of the thermal and electrical connections to the planes power dissipated by adjacent components connect all the ground and power balls to the respective planes with one via per ball. using fewer vias to connect the package to the planes reduces the thermal performance. thinner planes also reduce the thermal performance. when the clearance between the vias leave the planes virtually disconnected, the ther mal performance is also greatly reduced. table 12. thermal characteristics for 324-pin pbga (1) symbol c parameter conditions value unit r ? ja cc d junction-to-ambient, natural convection (2) single layer board - 1s 31 c/w r ? ja cc d junction-to-ambient, natural convection (2) four layer board - 2s2p 23 c/w r ? jma cc d junction-to-moving-air, ambient (2) at 200 ft./min., single layer board 23 c/w r ? jma cc d junction-to-moving-air, ambient (2) at 200 ft./min., four layer board 2s2p 17 c/w r ? jb cc d junction-to-board (3) 11 c/w r ? jctop cc d junction-to-case (4) 7c/w ? jt cc d junction-to-package top, natural convection (5) 2c/w 1. thermal characteristics ar e targets based on simulation that are s ubject to change per devic e characterization. 2. junction-to-ambient thermal resist ance determined per jedec jesd51-3 and jesd51-6. thermal test board meets jedec specification for this package. 3. junction-to-board thermal re sistance determined per jedec jesd51-8. ther mal test board meets jedec specification for the specified package. 4. junction-to-case at the top of the package determined using mil-std 883 method 1012.1. the cold plate temperature is used for the case temperature. reported value incl udes the thermal resistance of the interface layer. 5. thermal characterization parameter indicating the tem perature difference between the package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the therma l characterization pa rameter is written as psi-jt.
electrical characteristics spc564a74l7, spc564a80b4, spc564a80l7 86/157 doc id 15399 rev 9 as a general rule, the value obtained on a single-layer board is within the normal range for the tightly packed printed circuit board. the value obtained on a board with the internal planes is usually within the normal range if the application board has: one oz. (35 micron nominal thickness) internal planes components are well separated overall power dissipation on the board is less than 0.02 w/cm 2 the thermal performance of any component depends on the power dissipation of the surrounding components. in addition, the ambient temperature varies widely within the application. for many natural convection and es pecially closed box applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device. at a known board temperature, the junction temperature is estimated using the following equation: equation 2 t j = t b + (r ? jb * p d ) where: t b = board temperature for the package perimeter ( o c) r ? jb = junction-to-board thermal resistance ( o c/w) per jesd51-8s p d = power dissipation in the package (w) when the heat loss from the package case to the air does not factor into the calculation, an acceptable value for the junction temperature is predictable. ensure the application board is similar to the thermal test condition, with the component soldered to a board with internal planes. the thermal resistance is expr essed as the sum of a junction-to-case thermal resistance plus a case-to-ambient thermal resistance: equation 3 r ? ja = r ? jc + r ? ca where: r ? ja = junction-to-ambient thermal resistance ( o c/w) r ? jc = junction-to-case thermal resistance ( o c/w) r ? ca = case to ambient thermal resistance ( o c/w) r ? jc is device related and is not affected by other factors. the thermal environment can be controlled to change the case-to-ambient thermal resistance, r ? ca . for example, change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. this description is most useful for packages with heat sinks where 90% of the heat flow is through the case to heat sink to ambient. for most packages, a better model is required. a more accurate two-resistor thermal model can be constructed from the junction-to-board thermal resistance and the junction-to-case thermal resistance. the junction-to-case thermal resistance describes when using a heat sink or where a substantial amount of heat is dissipated from the top of the package. the junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit
spc564a74l7, spc564a80b4, spc564a80l7 electrical characteristics doc id 15399 rev 9 87/157 board. this model can be used to generate simple estimations and for computational fluid dynamics (cfd) thermal models. to determine the junction temperature of the device in the application on a prototype board, use the thermal characterization parameter ( ? jt ) to determine the junction temperature by measuring the temperature at the top center of the package case using the following equation: equation 4 t j = t t + ( ? jt x p d ) where: t t = thermocouple temperature on top of the package ( o c) ? jt = thermal characterization parameter ( o c/w) p d = power dissipation in the package (w) the thermal characterization parameter is measured in compliance with the jesd51-2 specification using a 40-gauge type t thermocouple epoxied to the top center of the package case. position the thermocouple so that the thermocouple junction rests on the package. place a small amount of epoxy on the thermocouple junction and approximately 1 mm of wire extending from the junction. pl ace the thermocouple wire flat against the package case to avoid measurement errors caused by the cooling effects of the thermocouple wire. references: semiconductor equipment and materials international 3081 zanker road san jose, ca 95134 usa (408) 943-6900 mil-spec and eia/jesd (jedec) specificatio ns are available from global engineering documents at 800-854-7179 or 303-397-7956. jedec specifications are available on the web at http://www.jedec.org. c.e. triplett and b. joiner, ?an experimental characterization of a 272 pbga within an automotive engine controller module,? proceedings of semitherm, san diego, 1998, pp. 47-54. g. kromann, s. shidore, and s. addison, ?thermal modeling of a pbga for air-cooled applications?, electronic packaging and production, pp. 53-58, march 1998. b. joiner and v. adams, ?measurement and simulation of junction to board thermal resistance and its application in thermal modeling,? proceedings of semitherm, san diego, 1999, pp. 212-220.
electrical characteristics spc564a74l7, spc564a80b4, spc564a80l7 88/157 doc id 15399 rev 9 3.4 emi (electromagnetic in terference) characteristics 3.5 electrostatic discharge (esd) characteristics table 13. emi testing specifications (1) symbol parameter conditions clocks frequency range level (max) unit radiated emissions, electric field v re_tem v ddreg =5.25v; t a =25c 150 khz ? 30 mhz rbw 9 khz, step size 5 khz 30 mhz ? 1 ghz - rbw 120 khz, step size 80 khz 16 mhz crystal 40 mhz bus no pll frequency modulation 150 khz ? 50 mhz 20 db ? v 50 ? 150 mhz 20 150 ? 500 mhz 26 500 ? 1000 mhz 26 iec level k ? sae level 3 ? 16 mhz crystal 40 mhz bus 2% pll frequency modulation 150 khz? 50 mhz 13 db ? v 50 ? 150 mhz 13 150 ? 500 mhz 11 500 ? 1000 mhz 13 iec level l ? sae level 2 ? 1. emi testing and i/o port waveforms per sae j1752/3 issued 1995-03 and iec 61967-2. table 14. esd ratings (1),(2) symbol parameter conditions value unit ? sr esd for human body model (hbm) ? 2000 v r1 sr hbm circuit description ? 1500 ? c sr ? 100 pf ?sr esd for field induced charge model (fdcm) all pins 500 v corner pins 750 ? sr number of pulses per pin positive pulses (hbm) 1 ? negative pulses (hbm) 1 ? ? sr number of pulses ? 1 ? 1. all esd testing is in conformity with cdf-aec-q100 stress test qualification fo r automotive grade integrated circuits. 2. device failure is defined as: ?if afte r exposure to esd pulses, the device does not meet the device specification requirements, which includes the complete dc parametr ic and functional testing at room temperature and hot temperature.?
spc564a74l7, spc564a80b4, spc564a80l7 electrical characteristics doc id 15399 rev 9 89/157 3.6 power management control (pmc) and power on reset (por) electrical specifications table 15. pmc operating conditions and external regulators supply voltage id name parameter min typ max unit 1 jtemp sr ? junction temperature ?40 27 150 c 2 vddreg sr ? pmc 5 v supply voltage v ddreg 4.75 5 5.25 v 3vddsr? core supply voltage 1.2 v v dd when external regulator is used without disabling the internal regulator (pmc unit turned on, lvi monitor active) (1) 1.26 (2) 1.3 1.32 v 3a ? sr ? core supply voltage 1.2 v v dd when external regulator is used with a disabled internal regulator (pmc unit turned-off, lvi monitor disabled) 1.14 1.2 1.32 v 4ivddsr? voltage regulator core supply maximum required dc output current 445 ? ? ma 5 vdd33 sr ? regulated 3.3 v supply voltage when external regulator is used without disabling the internal regulator (pmc unit turned-on, internal 3.3v regulator enabled, lvi monitor active) (3) 3.3 3.45 3.6 v 5a ? sr ? regulated 3.3 v supply voltage when external regulator is used with a disabled internal regulator (pmc unit turned-off, lvi monitor disabled) 33.33.6v 6?sr? voltage regulator 3.3 v supply maximum required dc output current 80 ? ? ma 1. an internal regulator controller can be used to regulate core supply. 2. the minimum supply required for the part to exit reset and enter in normal run mode is 1.28 v. 3. an internal regulator can be used to regulate 3.3 v supply. table 16. pmc electrical characteristics id name parameter min typ max unit notes 1 vbg cc c nominal bandgap voltage reference ?1.219? v 1a ? cc p untrimmed bandgap reference voltage vbg - 7% vbg vbg + 6% v 1b ? cc p trimmed bandgap reference voltage (5 v, 27 c) vbg -10mv vbg vbg + 10mv v 1c ? cc c bandgap reference temperature variation ?100?ppm/c 1d ? cc c bandgap reference supply voltage variation ? 3000 ? ppm/v
electrical characteristics spc564a74l7, spc564a80b4, spc564a80l7 90/157 doc id 15399 rev 9 2vddccc nominal v dd core supply internal regulator target dc output voltage (1) ?1.28?v 2a ? cc p nominal v dd core supply internal regulator target dc output voltage variation at power-on reset vdd - 6% vdd vdd + 10% v 2b ? cc p nominal v dd core supply internal regulator target dc output voltage variation after power-on reset vdd - 10% (2) vdd vdd + 3% v 2c ? cc c trimming step vdd ? 20 ? mv 2d ivrcctl cc c voltage regulator controller for core supply maximum dc output current 20 ? ? ma 3 lvi1p2 cc c nominal lvi for rising core supply (3) ?1.160? v 3a ? cc c variation of lvi for rising core supply at power-on reset 1.120 1.200 1.280 v see note (4) 3b ? cc c variation of lvi for rising core supply after power-on reset lvi1p2 - 3% lvi1p2 lvi1p2 + 3% vsee note (4) 3c ? cc c trimming step lvi core supply ?20?mv 3d lvi1p2_h cc c lvi core supply hysteresis ? 40 ? mv 4 por1.2v_r cc c por 1.2 v rising ? 0.709 ? v 4a ? cc c por 1.2 v rising variation por1.2v_r - 35% por1.2v_r por1.2v_r + 35% v 4b por1.2v_f cc c por 1.2 v falling ? 0.638 ? v 4c ? cc c por 1.2 v falling variation por1.2v_f - 35% por1.2v_f por1.2v_f + 35% v 5 vdd33 cc c nominal 3.3 v supply internal regulator dc output voltage ?3.39?v 5a ? cc p nominal 3.3 v supply internal regulator dc output voltage variation at power- on reset vdd33 - 8.5% vdd33 vdd3 + 7% v see note (5) 5b ? cc p nominal 3.3 v supply internal regulator dc output voltage variation power-on reset vdd33 - 7.5% vdd33 vdd33 + 7% v with internal load up to idd3p3 table 16. pmc electrical characteristics (continued) id name parameter min typ max unit notes
spc564a74l7, spc564a80b4, spc564a80l7 electrical characteristics doc id 15399 rev 9 91/157 5c ? cc d voltage regulator 3.3 v output impedance at maximum dc load ?? 2 ? 5d idd3p3 cc p voltage regulator 3.3 v maximum dc output current (internal regulator enabled) (6) 80 (7) ??ma 5e vdd33 ilim cc c voltage regulator 3.3 v dc current limit ?130?ma 6 lvi3p3 cc c nominal lvi for rising 3.3 v supply ?3.090? v the lvi3p3 specs are also valid for the vddeh lv i 6a ? cc c variation of lvi for rising 3.3 v supply at power-on reset lvi3p3 - 6% lvi3p3 lvi3p3 + 6% vsee note (8) 6b ? cc c variation of lvi for rising 3.3 v supply after power-on reset lvi3p3 - 3% lvi3p3 lvi3p3 + 3% vsee note (8) 6c ? cc c trimming step lvi 3.3 v ? 20 ? mv 6d lvi3p3_h cc c lvi 3.3 v hysteresis ? 60 ? mv 7 por3.3v_r cc c nominal por for rising 3.3 v supply ?2.07?v the 3.3v por specs are also valid for the v ddeh por 7a ? cc c variation of por for rising 3.3 v supply por3.3v_r- 35% por3.3v_r por3.3v_r + 35% v 7b por3.3v_f cc c nominal por for falling 3.3 v supply ?1.95?v 7c ? cc c variation of por for falling 3.3 v supply por3.3v_f - 35% por3.3v_f por3.3v_f + 35% v 8 lvi5p0 cc c nominal lvi for rising 5 v v ddreg supply ?4.290? v 8a ? cc c variation of lvi for rising 5 v v ddreg supply at power-on reset lvi5p0 - 6% lvi5p0 lvi5p0 + 6% v 8b ? cc c variation of lvi for rising 5 v v ddre g supply power-on reset lvi5p0 - 3% lvi5p0 lvi5p0 + 3% v 8c ? cc c trimming step lvi 5 v ? 20 ? mv 8d lvi5p0_h cc c lvi 5 v hysteresis ? 60 ? mv table 16. pmc electrical characteristics (continued) id name parameter min typ max unit notes
electrical characteristics spc564a74l7, spc564a80b4, spc564a80l7 92/157 doc id 15399 rev 9 3.6.1 regulator example in designs where the spc564a80 microcontroller? s internal regulators are used, a ballast is required for generation of the 1.2 v internal supply. no ballast is required when an external 1.2 v supply is used. 9 por5v_r cc c nominal por for rising 5 v v ddreg supply ?2.67?v 9a ? cc c variation of por for rising 5v v ddreg supply por5v_r - 35% por5v_r por5v_r + 50% v 9b por5v_f cc c nominal por for falling 5 v v ddreg supply ?2.47?v 9c ? cc c variation of por for falling 5v v ddreg supply por5v_f - 35% por5v_f por5v_f + 50% v 1. using external ballast transistor. 2. min range is extended to 10% sinc e lvi1p2 is reprogrammed from 1.2 v to 1.16 v after power-on reset. 3. lvi for falling supply is calculat ed as lvi rising ? lvi hysteresis. 4. lvi1p2 tracks dc target variati on of internal vdd regulator. minimum and maximum lvi1p2 correspond to minimum and maximum vdd dc target respectively. 5. minimum loading (<10 ma) for reading trim values from flash, powering internal rc oscillator, and io consumption during por. 6. no external load is allowed, except fo r use as a reference for an external tool. 7. this value is valid only when the internal regulator is bypassed. when the internal regulator is enabled, the maximum external load allowed on the nexus pads is 30 pf at 40 mhz. 8. lvi3p3 tracks dc target variation of internal vdd33 regulator. minimum and maximum lvi3p3 correspond to minimum and maximum vdd33 dc target respectively. table 16. pmc electrical characteristics (continued) id name parameter min typ max unit notes
spc564a74l7, spc564a80b4, spc564a80l7 electrical characteristics doc id 15399 rev 9 93/157 figure 8. core voltage regulator controller external components preferred configuration mcu the bypass transistor must be operated out of saturation region. mandatory decoupling capacitor network v ddreg v rcctl v dd v ss vrcctl capacitor and resistor is required ce cd cb rb cc creg rc the resistor may or may not be required. this depends on the allowable power dissipation of the npn bypass transistor device. the resistor may be used to limit the in-rush current at power on. re keep parasitic inductance under 20nh table 17. spc564a80 external network specification external network parameter min typ max comment t1 njd2873 or bcp68 only cb 1.1 ? f2.2 ? f2.97 ? f x7r,-50%/+35% ce 3*2.35 ? f+5 ? f3*4.7 ? f+10 ? f3*6.35 ? f+13.5 ? f x7r, -50%/+35% equivalent esr of ce capacitors 5m 50m cd 4*50nf 4*100nf 4*135nf x7r, -50%/+35% rb 9 10 11 +/-10% re 0.252 0.280 0.308 +/-10% creg 10 ? f it depends on external vreg. cc 5 ? f10 ? f13.5 ? f x7r, -50%/+35% rc 1.1 5.6 may or may not be required. it depends on the allowable power dissipation of t1. ? ? ? ? ? ? ? ? ? ?
electrical characteristics spc564a74l7, spc564a80b4, spc564a80l7 94/157 doc id 15399 rev 9 3.6.2 recommended power transistors the following npn transistors are recommended for use with the on-chip voltage regulator controller: on semiconductor tm bcp68t1 or njd2873 as we ll as philips semiconductor tm bcp68. the collector of the external transistor is preferably connected to the same voltage supply source as the output stage of the regulator. 3.7 power up/down sequencing there is no power sequencing required among power sources during power up and power down, in order to operate within specification. although there are no power up/down sequencing requirements to prevent issues such as latch-up or excessive current spikes the state of the i/o pins during power up/down varies according to ta b l e 1 9 for all pins with fast pads, and ta bl e 2 0 for all pins with medium, slow, and multi-voltage pads. table 18. recommended operating characteristics symbol parameter value unit h fe ( ? ) dc current gain (beta) 60 ? 550 ? p d absolute minimum power dissipation >1.0 (1.5 preferred) w i cmaxdc minimum peak collector current 1.0 a vce sat collector-to-emitter saturation voltage 200 ? 600 (1) 1. adjust resistor at bipolar transistor collector for 3.3 v/5.0 v to avoid vce < vce sat . mv v be base-to-emitter voltage 0.4 ? 1.0 v table 19. power sequence pin states (fast pads) v dde v rc33 v dd pad state low x x low v dde low x high v dde v rc33 low high impedance v dde v rc33 v dd functional table 20. power sequence pin states (medium, slow, and multi-voltage pads) v ddeh v dd pad state low x low v ddeh low high impedance v ddeh v dd functional
spc564a74l7, spc564a80b4, spc564a80l7 electrical characteristics doc id 15399 rev 9 95/157 3.8 dc electrical specifications table 21. dc electrical specifications symbol c parameter conditions value unit min typ max v dd sr ? core supply voltage ? 1.14 1.32 v v dde sr ? i/o supply voltage ? 1.62 3.6 v v ddeh sr ? i/o supply voltage ? 3.0 5.25 v v dde-eh sr ? i/o supply voltage ? 3.0 5.25 v v rc33 sr ? 3.3 v regulated voltage (1) ?3.0?3.6v v dda sr ? analog supply voltage ? 4.75 (2) ?5.25v v indc sr ? analog input voltage ? v ssa -0.3 ? v dda +0.3 v v ss ? v ssa sr ? v ss differential voltage ? ?100 ? 100 mv v rl sr ? analog reference low voltage ?v ssa ?v ssa +0.1 v v rl ? v ssa sr ? vrl differential voltage ? ?100 ? 100 mv v rh sr ? analog reference high voltage ?v dda -0.1 ? v dda v v rh ? v rl sr ? v ref differential voltage ? 4.75 ? 5.25 v v ddf sr ? flash operating voltage (3) ? 1.14 ? 1.32 v v flash (4) sr ? flash read voltage ? 3.0 ? 3.6 v v stby sr ? sram standby voltage keep-out range: 1.2v? 2v unregulated mode 0.95 ? 1.2 v regulated mode 2.0 ? 5.5 v ddreg sr ? voltage regulator supply voltage ? 4.75 ? 5.25 v v ddpll sr ? clock synthesizer operating voltage ? 1.14 ? 1.32 v v sspll ? v ss sr ? v sspll to v ss differential voltage ? ?100 ? 100 mv v il_s cc c slow/medium i/o pad input low voltage hysteresis enabled v ss -0.3 ? 0.35*v ddeh v p hysteresis disabled v ss -0.3 ? 0.40*v ddeh
electrical characteristics spc564a74l7, spc564a80b4, spc564a80l7 96/157 doc id 15399 rev 9 v il_f cc c fast pad i/o input low voltage hysteresis enabled v ss -0.3 ? 0.35*v dde v p hysteresis disabled v ss -0.3 ? 0.40*v dde v il_ls cc c multi-voltage i/o pad input low voltage in low-swing- mode (5),(6),(7),(8) hysteresis enabled v ss -0.3 ? 0.8 v p hysteresis disabled v ss -0.3 ? 1.1 v il_hs cc c multi-voltage pad i/o input low voltage in high-swing-mode hysteresis enabled v ss -0.3 ? 0.35 v ddeh v p hysteresis disabled v ss -0.3 ? 0.4 v ddeh v ih_s cc c slow/medium pad i/o input high voltage (9) hysteresis enabled 0.65 v ddeh ?v ddeh +0.3 v p hysteresis disabled 0.55 v ddeh ?v ddeh +0.3 v ih_f cc c fast i/o input high voltage hysteresis enabled 0.65 v dde ?v dde +0.3 v p hysteresis disabled 0.58 v dde ?v dde +0.3 v ih_ls cc c multi-voltage pad i/o input high voltage in low-swing- mode (5),(6),(7),(8) hysteresis enabled 2.5 ? v ddeh +0.3 v p hysteresis disabled 2.2 ? v ddeh +0.3 v ih_hs cc c multi-voltage i/o input high voltage in high- swing-mode hysteresis enabled 0.65 v ddeh ?v ddeh +0.3 v p hysteresis disabled 0.55 v ddeh ?v ddeh +0.3 v ol_s cc p slow/medium pad i/o output low voltage (9) ? ? 0.2*v ddeh v v ol_f cc p fast i/o output low voltage (9) ? ? 0.2*v dde v v ol_ls cc p multi-voltage pad i/o output low voltage in low-swing mode (5),(6),(7),(8),(9) ?? 0.6v table 21. dc electrical specifications (continued) symbol c parameter conditions value unit min typ max
spc564a74l7, spc564a80b4, spc564a80l7 electrical characteristics doc id 15399 rev 9 97/157 v ol_hs cc p multi-voltage pad i/o output low voltage in high-swing mode (9) ? ? 0.2*v ddeh v v oh_s cc p slow/medium pad i/o output high voltage (9) 0.8 v ddeh ??v v oh_f cc p fast pad i/o output high voltage (9) 0.8 v dde ??v v oh_ls cc p multi-voltage pad i/o output high voltage in low-swing mode (5),(6),(7),(8) i oh_ls = 0.5 ma 2.1 3.1 3.7 v v oh_hs cc p multi-voltage pad i/o output high voltage in high-swing mode (9) 0.8 v ddeh ??v v hys_s cc c slow/medium/multi- voltage i/o input hysteresis ? 0.1 * v ddeh ??v v hys_f cc c fast i/o input hysteresis ? 0.1 * v dde ??v v hys_ls cc c low-swing-mode multi- voltage i/o input hysteresis hysteresis enabled 0.25 ? ? v i dd +i ddpll cc p operating current 1.2 v supplies v dd at 1.32 v at 80 mhz ? 380 ma p v dd at 1.32v at 120 mhz ? 400 ma p v dd at 1.32v at 150 mhz ? 445 ma i ddstby cc t operating current 0.95- 1.2 v v stby at 55 o c ? 35 100 ? a t operating current 2? 5.5 v v stby at 55 o c ? 45 110 ? a i ddstby27 cc p operating current 0.95- 1.2 v v stby 27 o c 25 90 ? a p operating current 2- 5.5 v v stby 27 o c 35 100 ? a table 21. dc electrical specifications (continued) symbol c parameter conditions value unit min typ max
electrical characteristics spc564a74l7, spc564a80b4, spc564a80l7 98/157 doc id 15399 rev 9 i ddstby150 cc p operating current 0.95- 1.2 v v stby 150 o c ? 790 2000 ? a p operating current 2? 5.5 v v stby at 150 o c ? 760 2000 ? a i ddslow i ddstop cc pv dd low-power mode operating current at 1.32 v slow mode (10) ? 191 ma p stop mode (11) ? 190 i dd33 cc c operating current 3.3 v supplies v rc33 (1) , (12) ?60ma i dda i ref i ddreg cc p operating current 5.0 v supplies v dda ? ? 30.0 ma p analog reference supply current (transient) ?? 1.0 cv ddreg ??70 (13) i ddh1 i ddh4 i ddh6 i ddh7 i dd7 i ddh9 i dd12 cc d operating current v dde (14) supplies v ddeh1 ?? see note (14) ma dv ddeh4 ?? dv ddeh6 ?? dv ddeh7 ?? dv dde7 ?? dv ddeh9 ?? dv dde12 ?? i act_s cc c slow/medium i/o weak pull up/down current (15) 3.0 v ? 3.6 v 15 ? 95 ? a p 4.75 v ? 5.5 v 35 ? 200 i act_f cc d fast i/o weak pull up/down current (15) 1.62 v ? 1.98 v 36 ? 120 ? a d 2.25 v ? 2.75 v 34 ? 139 d 3.0 v ? 3.6 v 42 ? 158 i act_mv_pu cc c multi-voltage pad weak pullup current v dde = 3.0?3.6 v (5) , multiv pad, high swing mode only 10 ? 75 ? a p 4.75 v ? 5.25 v 25 ? 200 table 21. dc electrical specifications (continued) symbol c parameter conditions value unit min typ max
spc564a74l7, spc564a80b4, spc564a80l7 electrical characteristics doc id 15399 rev 9 99/157 i act_mv_pd cc c multivoltage pad weak pulldown current v dde = 3.0?3.6 v (5) , multiv pad, high swing mode only 10 ? 60 ? a p 4.75 v ? 5.25 v 25 ? 200 i inact_d cc p i/o input leakage current (16) ? ?2.5 ? 2.5 ? a i ic sr t dc injection current (per pin) ? ?1.0 ? 1.0 ma i inact_a sr p analog input current, channel off, an[0:7] (17) ? ?250 ? 250 na p analog input current, channel off, all other analog pins (17) ? ?150 ? 150 c l cc d load capacitance (fast i/o) (18) dsc(pcr[8:9]) = 0b00 ?10 pf d dsc(pcr[8:9]) = 0b01 ?20 d dsc(pcr[8:9]) = 0b10 ?30 d dsc(pcr[8:9]) = 0b11 ?50 c in cc d input capacitance (digital pins) ?? 7pf c in_a cc d input capacitance (analog pins) ?? 10pf c in_m cc d input capacitance (digital and analog pins (19) ) ?? 12pf r pupd200k sr p weak pull-up/down resistance (20) , 200 k ? option ? 130 ? 280 k ? r pupd100k sr p weak pull-up/down resistance (20) , 100 k ? option ? 65 ? 140 k ? table 21. dc electrical specifications (continued) symbol c parameter conditions value unit min typ max
electrical characteristics spc564a74l7, spc564a80b4, spc564a80l7 100/157 doc id 15399 rev 9 r pupd5k sr c weak pull-up/down resistance (20) , 5k ? option 5v5% supply 1.4 ? 7.5 k ? r pupdmtch cc c pull-up/down resistance matching ratios (100k/200k) pull-up and pull-down resistances both enabled and settings are equal. ?2.5 ? 2.5 % t a (t l to t h )sr? operating temperature range - ambient (packaged) ? ?40.0 125.0 ? c ?sr? slew rate on power supply pins ?? 25v/ms 1. these specifications apply when v rc33 is supplied externally , after disabling the internal regulator (v ddreg = 0). 2. adc is functional with 4 v ? v dda ? 4.75 v but with derated accuracy. this means the adc will continue to function at full speed with no undesirable behavior, but the accuracy will be degraded. 3. the v ddf supply is connected to v dd in the package substrate. this specificat ion applies to calibration package devices only. 4. v flash is only available in the calibration package. 5. power supply for multi-voltage pads cannot be below 4.5 v when in low-swing mode. 6. the slew rate (src) setting must be 0b11 when in low-swing mode. 7. while in low-swing mode there are no restri ctions in transition ing to high-swing mode. 8. pin in low-swing mode can accept a 5 v input. 9. all v ol /v oh values 100% tested with 2 ma load except where noted. 10. bypass mode, system clock at 1 mhz (usi ng system clock divider), pll shut down, cpu running simple executive code, 4 x adc conversion every 10 ms, 2 x pw m channels 1 khz, all other modules stopped. 11. bypass mode, system clock at 1 mhz (u sing system clock divider), cpu stopped, pit running, all other modules stopped. 12. this current will be consumed for external regulation and inte rnal regulation, when 3.3v regul ator is switched off by shadow flash 13. if 1.2v and 3.3v internal regulators are on,then iddreg=70ma if supply is external that is 3.3v in ternal regulator is off, then iddreg=15ma 14. power requirements for each i/o segment are dependent on t he frequency of operation and load of the i/o pins on a particular i/o segment, and the voltage of the i/o segment. see table 22 for values to calculate power dissipation for specific operation. the total power cons umption of an i/o segment is the sum of the individual power consumptions for each pin on the segment. 15. absolute value of current, measured at v il and v ih . 16. weak pull up/down inactive. measured at v dde = 3.6 v and v ddeh = 5.25 v. applies to fast, slow, and medium pads. 17. maximum leakage occurs at maximum o perating temperature. leakage current decr eases by approximately one-half for each 8 to 12 o c, in the ambient temperature range of 50 to 125 o c. applies to analog pads. 18. applies to clkout, external bus pins, and nexus pins. 19. applies to the fck, sdi, sdo, and sds pins. 20. this programmable option applies onl y to eqadc differential input channel s and is used for biasing and sensor diagnostics. table 21. dc electrical specifications (continued) symbol c parameter conditions value unit min typ max
spc564a74l7, spc564a80b4, spc564a80l7 electrical characteristics doc id 15399 rev 9 101/157 3.9 i/o pad current specifications the power consumption of an i/o segment depends on the usage of the pins on a particular segment. the power consumption is the sum of all output pin currents for a particular segment. the output pin current can be calculated from ta bl e 2 2 based on the voltage, frequency, and load on the pin. use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in ta b l e 2 2 . table 22. i/o pad average i dde specifications (1) pad type symbol c period (ns) load (2) (pf) v dde (v) drive/slew rate select i dde avg (ma) (3) i dde rms (ma) slow i drv_ssr_hv cc d 37 50 5.5 11 9 ? cc d 130 50 5.5 01 2.5 ? cc d 650 50 5.5 00 0.5 ? cc d 840 200 5.5 00 1.5 ? medium i drv_msr_hv cc d 24 50 5.5 11 14 ? cc d 62 50 5.5 01 5.3 ? cc d 317 50 5.5 00 1.1 ? cc d 425 200 5.5 00 3 ? fast i drv_fc cc d 10 50 3.6 11 22.7 68.3 cc d 10 30 3.6 10 12.1 41.1 cc d 10 20 3.6 01 8.3 27.7 cc d 10 10 3.6 00 4.44 14.3 cc d 10 50 1.98 11 12.5 31 cc d 10 30 1.98 10 7.3 18.6 cc d 10 20 1.98 01 5.42 12.6 cc d 10 10 1.98 00 2.84 6.4 multiv (high swing mode) i drv_multv_hv cc d 20 50 5.5 11 9 ? cc d 30 50 5.5 01 6.1 ? cc d 117 50 5.5 00 2.3 ? cc d 212 200 5.5 00 5.8 ? multiv (low swing mode) i drv_multv_hv cc d 30 30 5.5 11 3.4 ? 1. numbers from simulations at best case process, 150 c. 2. all loads are lumped. 3. average current is for pad configured as output only.
electrical characteristics spc564a74l7, spc564a80b4, spc564a80l7 102/157 doc id 15399 rev 9 3.9.1 i/o pad v rc33 current specifications the power consumption of the v rc33 supply is dependent on the usage of the pins on all i/o segments. the power consumption is the sum of all input and output pin v rc33 currents for all i/o segments. the output pin v rc33 current can be calculated from ta b l e 2 3 based on the voltage, frequency, and load on all fast pad pins. the input pin v rc33 current can be calculated from ta bl e 2 3 based on the voltage, frequency, and load on all medium-speed pads. use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in ta bl e 2 3 . table 23. i/o pad v rc33 average i dde specifications (1) pad type symbol c period (ns) load (2) (pf) drive select i dd33 avg (a) i dd33 rms (a) slow i drv_ssr_hv cc d 100 50 11 0.8 235.7 cc d 200 50 01 0.04 87.4 cc d 800 50 00 0.06 47.4 cc d 800 200 00 0.009 47 medium i drv_msr_hv cc d 40 50 11 2.75 258 cc d 100 50 01 0.11 76.5 cc d 500 50 00 0.02 56.2 cc d 500 200 00 0.01 56.2 multiv (3) (high swing mode) i drv_multv_hv cc d 20 50 11 33.4 35.4 cc d 30 50 01 33.4 34.8 cc d 117 50 00 33.4 33.8 cc d 212 200 00 33.4 33.7 multiv (4) (low swing mode) i drv_multv_hv cc d 30 30 11 33.4 34.9 1. these are typical values that are estimated from simulation and not tested . currents apply to output pins only. 2. all loads are lumped. 3. average current is for pad configured as output only. 4. in low swing mode, multi-voltage pads must operate in highest slew rate setting.
spc564a74l7, spc564a80b4, spc564a80l7 electrical characteristics doc id 15399 rev 9 103/157 3.9.2 lvds pad specifications lvds pads are implemented to support the ms c (microsecond channel) protocol which is an enhanced feature of the dspi module. the lvds pads are compliant with lvds specifications and support data rates up to 50 mhz. table 24. v rc33 pad average dc current (1) pad type symbol c period (ns) load (2) (pf) v rc33 (v) v dde (v) drive select i dd33 avg (a) i dd33 rms (a) fast i drv_fc cc d 10 50 3.6 3.6 11 2.35 6.12 cc d 10 30 3.6 3.6 10 1.75 4.3 cc d 10 20 3.6 3.6 01 1.41 3.43 cc d 10 10 3.6 3.6 00 1.06 2.9 cc d 10 50 3.6 1.98 11 1.75 4.56 cc d 10 30 3.6 1.98 10 1.32 3.44 cc d 10 20 3.6 1.98 01 1.14 2.95 cc d 10 10 3.6 1.98 00 0.95 2.62 1. these are typical values that are estimated from si mulation and not tested. currents apply to output pins only. 2. all loads are lumped. table 25. dspi lvds pad specification # characteristic symbol c condition min. value typ. value max. value unit data rate 4 data frequency f lvdsclk cc d ? 50 mhz driver specs 5 differential output voltage v od cc p src=0b00 or 0b11 150 400 mv cc p src=0b01 90 320 cc p src=0b10 160 480 6 common mode voltage (lvds), vos v od cc p 1.06 1.2 1.39 v 7 rise/fall time t r /t f cc d ? 2 ns 8 propagation delay (low to high) t plh cc d 4 ns 9 propagation delay (high to low) t phl cc d ? 4 ns
electrical characteristics spc564a74l7, spc564a80b4, spc564a80l7 104/157 doc id 15399 rev 9 3.10 oscillator and pllmrfm electrical characteristics 10 delay (h/l), sync mode t pdsync cc d 4 ns 11 delay, z to normal (high/low) t dz cc d ? 500 ns 12 diff skew itphla-tplhbi or itplhb-tphlai t skew cc d ? 0.5 ns termination 13 trans. line (differential zo) cc d ? 95 100 105 14 temperature cc d ?40 150 ? c table 25. dspi lvds pad specification (continued) # characteristic symbol c condition min. value typ. value max. value unit ? f ref_crystal f ref_ext cc d pll reference frequency range (1) crystal reference 440 mhz c external reference 480 f pll_in cc p phase detector input frequency range (after pre-divider) ?416mhz f vco cc p vco frequency range ? 256 512 mhz f sys cc c on-chip pll frequency (2) ? 16 150 mhz f sys cc t system frequency in bypass mode (2) crystal reference 440 mhz p external reference 080 t cyc cc d system clock period ? ? 1 / f sys ns f lorl f lorh cc d loss of reference frequency window (3) lower limit 1.6 3.7 mhz d upper limit 24 56 f scm cc p self-clocked mode frequency (4),(5) ? 1.2 72.25 mhz
spc564a74l7, spc564a80b4, spc564a80l7 electrical characteristics doc id 15399 rev 9 105/157 c jitter cc t clkout period jitter (6),(7),(8),(9) peak-to-peak (clock edge to clock edge) f sys maximum ?5 5 % f clkout t long-term jitter (avg. over 2 ms interval) ?6 6 ns t cst cc t crystal start-up time (10), (11) ??10ms v ihext cc t extal input high voltage crystal mode (12) vxtal + 0.4 ? v t external reference (12), (13) v rc33 /2 + 0.4 v rc33 v ilext cc t extal input low voltage crystal mode (12) ? vxtal - 0.4 v t external reference (12), (13) 0 v rc33 /2 - 0.4 ? cc t xtal load capacitance (10) 4mhz 5 30 pf 8mhz 5 26 12 mhz 5 23 16 mhz 5 19 20 mhz 5 16 40 mhz 5 8 t lpll cc p pll lock time (10), (14) ? ? 200 ? s t dc cc t duty cycle of reference ?4060% f lck cc t frequency lock range ? ?6 6 % f sys f ul cc t frequency un-lock range ? ?18 18 % f sys f cs f ds cc d modulation depth center spread 0.25 4.0 %f sys d down spread ?0.5 ?8.0 f mod cc d modulation frequency (15) ? ? 100 khz 1. considering operation with pll not bypassed. 2. all internal registers retain data at 0 hz. 3. ?loss of reference frequency? window is the reference frequency range outside of which the pll is in self clocked mode. 4. self clocked mode frequency is the frequency that the pll op erates at when the reference frequency falls outside the f lor window. table 26. pllmrfm electrical specifications (v ddpll = 1.08 v to 3.6 v, v ss = v sspll = 0 v, t a = t l to t h ) (continued) symbol c parameter conditions value unit min max
electrical characteristics spc564a74l7, spc564a80b4, spc564a80l7 106/157 doc id 15399 rev 9 3.11 temperature sensor electrical characteristics 3.12 eqadc electrical characteristics 5. f vco self clock range is 20?150 mhz. f scm represents f sys after pll output divider (erfd) of 2 through 16 in enhanced mode. 6. this value is determined by the crystal manufacturer and board design. 7. jitter is the average deviation from t he programmed frequency measured over t he specified interval at maximum f sys . measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. noise injected into the pll circuitry via v ddpll and v sspll and variation in crystal osci llator frequency increase the c jitter percentage for a given interval. 8. proper pc board layout procedures must be followed to achieve specifications. 9. values are with frequency modulati on disabled. if frequency modulation is enabled, jitter is the sum of c jitter and either f cs or f ds (depending on whether center spread or down spread modulation is enabled). 10. this value is determined by the crystal manufacturer and board design. for 4 mhz to 40 mhz crystals specified for this pll, load capacitors should not exceed these limits. 11. proper pc board layout procedures must be followed to achieve specifications. 12. this parameter is guaranteed by design rather than 100% tested. 13. v ihext cannot exceed v rc33 in external reference mode. 14. this specification applies to the period required for the p ll to relock after changing the mf d frequency control bits in the synthesizer control register (syncr). 15. modulation depth will be attenuated from depth setti ng when operating at modulation frequencies above 50 khz. table 27. temperature sensor electrical characteristics symbol c parameter conditions value unit min typical max ?ccc temperature monitoring range ?40 ? 150 c ? cc c sensitivity ? 6.3 ? mv/c ? cc p accuracy t j = ?40 to 150 c ?10 ? 10 c table 28. eqadc conversion specifications (operating) symbol c parameter value unit min max f adclk sr ? adc clock (adclk) frequency 2 16 mhz cc cc d conversion cycles 2+13 128+14 adclk cycles t sr cc c stop mode recovery time (1) ?10 ? s f adclk sr ? adc clock (adclk) frequency 2 16 mv 1. stop mode recovery time is the time from the setting of either of the enable bits in the adc control register to the time tha t the adc is ready to perform conversions.del ay from power up to full accuracy = 8 ms.
spc564a74l7, spc564a80b4, spc564a80l7 electrical characteristics doc id 15399 rev 9 107/157 table 29. eqadc single ended conversion specifications (operating) symbol c parameter value unit min max offnc cc c offset error withou t calibration 0 160 counts offwc cc c offset error with calibration ?4 4 counts gainnc cc c full scale gain error without calibration ?160 0 counts gainwc cc c full scale gain error with calibration ?4 4 counts i inj cc t disruptive input injection current (1), (2), (3), (4) ?3 3 ma e inj cc t incremental error d ue to injection current (5),(6) ?4 4 counts tue8 cc c total unadjusted error (tue) at 8 mhz ?4 4 (6) counts tue16 cc c total unadjusted error at 16 mhz ?8 8 counts 1. below disruptive current c onditions, the channel being stress ed has conversion values of 0x3ff for analog inputs greater then v rh and 0x0 for values less then v rl . other channels are not affected by non-disruptive conditions. 2. exceeding limit may cause c onversion error on stressed channels and on unstress ed channels. transitions within the limit do not affect device reliabil ity or cause permanent damage. 3. input must be current limited to the value specified. to determine the value of the requi red current-limiting resistor, calculate resistance values using v posclamp = v dda + 0.5 v and v negclamp = ? 0.3 v, then use the larger of the calculated values. 4. condition applies to two adjacen t pins at injection limits. 5. performance expected with production silicon. 6. all channels have same 10 k ? electrical characteristics spc564a74l7, spc564a80b4, spc564a80l7 108/157 doc id 15399 rev 9 gainvga2 (1) cc ? variable gain amplifier accuracy (gain=2) (2) cc d inl 8mhz adc ?5 5 counts cc d 16 mhz adc ?8 8 counts cc d dnl 8mhz adc ?3 3 counts cc d 16 mhz adc ?3 3 counts gainvga4 (1) cc ? variable gain amplifier accuracy (gain=4) (2) cc d inl 8mhz adc ?7 7 counts cc d 16 mhz adc ?8 8 counts cc d dnl 8mhz adc ?4 4 counts cc d 16 mhz adc ?4 4 counts diff max cc c maximum differential voltage (danx+ - danx-) or (danx- - danx+) (5) pregain set to 1x setting ? (vrh - vrl)/2 v diff max2 cc c pregain set to 2x setting ? (vrh - vrl)/4 v diff max4 cc c pregain set to 4x setting ? (vrh - vrl)/8 v diff cmv cc c differential input common mode voltage (danx- + danx+)/2 (5) ? (v rh + v rl )/2 - 5% (v rh + v rl )/2 + 5% v 1. applies only to differential channels. 2. variable gain is controlled by setting the pre_gain bits in the adc_acr1 -8 registers to select a gain factor of ? 1, ? 2, or ? 4. settings are for differential input only. tested at ? 1 gain. values for other settings are guaranteed by as indicated. 3. at v rh ? v rl = 5.12 v, one lsb = 1.25 mv. 4. guaranteed 10-bit mono tonicity. 5. voltages between vrl and vrh will not cause damage to the pins . however, they may not be converted accurately if the differential voltage is above the maximum differential voltage. in addition, conversion errors may occur if the common mode voltage of the differential signal violates the differential input common mode voltage specification. table 30. eqadc differential ended conversion specifications (operating) (continued) symbol c parameter value unit min max
spc564a74l7, spc564a80b4, spc564a80l7 electrical characteristics doc id 15399 rev 9 109/157 3.13 configuring sram wait states use the swsc field in the ecsm_mudcr register to specify an additional wait state for the device sram. by default, no wait state is added. please see the device reference manual for details. 3.14 platform flash controlle r electrical characteristics 3.15 flash memory electrical characteristics table 31. cutoff frequency for additional sram wait state (1) 1. max frequencies including 2% pll fm. swsc value 98 0 153 1 table 32. apc, rwsc, wwsc settings vs. frequency of operation (1),(2) 1. apc, rwsc and wwsc are fields in the flash memo ry biucr register used to specify wait states for address pipelining and read/ write accesses. illegal combinations ex ist?all entries must be taken from the same row. 2. tbd: to be defined. max. flash operating frequency (mhz) (3) 3. max frequencies including 2% pll fm. apc (4) 4. apc must be equal to rwsc. rwsc (4) wwsc 20 mhz 0b000 0b000 0b11 61 mhz 0b001 0b001 0b11 90 mhz 0b010 0b010 0b11 123 mhz 0b011 0b011 0b11 153 mhz 0b100 0b100 0b11 table 33. flash program and erase specifications (1) #symbolc parameter min. value typical value initial max (2) max (3) unit 1t dwprogram c c p double word (64 bits) program time ? 45 ? 500 ? s 2t pprogram c c p page program time ? 55 160 (4) 500 ? s 3t 16kpperase c c p 16 kb block pre-program and erase time ? 300 1000 5000 ms
electrical characteristics spc564a74l7, spc564a80b4, spc564a80l7 110/157 doc id 15399 rev 9 5t 64kpperase c c p 64 kb block pre-program and erase time ? 800 1800 5000 ms 6t 128kpperase c c p 128 kb block pre-program and erase time ? 1500 3000 7500 ms 7t 256kpperase c c p 256 kb block pre-program and erase time ? 3000 5300 15000 ms 8t psrt sr ? program suspend request rate (5) 100 ? ? ? ? s 9t esrt sr ? erase suspend request rate (6) 10 ms 1. typical program and erase times assume nominal supply values and operation at 25 o c. all times are subject to change pending device characterization. 2. initial factory condition: < 100 program/erase cycles, 25 o c, typical supply voltage, 80 mhz minimum system frequency. 3. the maximum erase time occurs after t he specified number of program /erase cycles. this maximu m value is characterized but not guaranteed. 4. page size is 128 bits (4 words). 5. time between program suspend resume and the next program suspend request. 6. time between erase suspend resume and the next erase suspend request. table 33. flash program and erase specifications (1) (continued) #symbolc parameter min. value typical value initial max (2) max (3) unit table 34. flash module life symbol c parameter conditions value unit min typ p/e cc c number of program/erase cycles per block for 16 kb, 48 kb, and 64 kbyte blocks over the operating temperature range (t j ) ? 100,000 ? p/e cycles p/e cc c number of program/erase cycles per block for 128 kbyte and 256 kbyte blocks over the operating temperature range (t j ) ? 1,000 100,000 p/e cycles data retention cc c minimum data retention at 85 ? c average ambient temperature (1) blocks with 0 ? 1,000 p/e cycles 20 ? years blocks with 1,001 ? 10,000 p/e cycles 10 ? years blocks with 10,001 ? 100,000 p/e cycles 5 ? years 1. ambient temperature averaged over dur ation of application, not to exc eed product operating temperature range.
spc564a74l7, spc564a80b4, spc564a80l7 electrical characteristics doc id 15399 rev 9 111/157 3.16 ac specifications 3.16.1 pad ac specifications table 35. pad ac specifications (5.0 v) (1) name c output delay (ns) (2),(3) low-to-high / high- to-low rise/fall edge (ns) (3),(4) drive load (pf) src/dsc min max min max msb,lsb medium (5),(6),(7) cc d 4.6/3.7 12/12 2.2/2.2 7/7 50 11 (8) n/a 10 (9) cc d 12/13 28/34 5.6/6 15/15 50 01 cc d 69/71 152/165 34/35 74/74 50 00 slow (7),(10) cc d 7.3/5.7 19/18 4 .4/4.3 14/14 50 11 (8) n/a 10 (9) cc d 26/27 61/69 13/13 34/34 50 01 cc d 137/142 320/330 72/74 164/164 50 00 multiv (11) (high swing mode) cc d 4.1/3.6 10.3/8.9 3.28/2.98 8/8 50 11 (8) n/a 10 (9) cc d 8.38/6.11 16/12.9 5 .48/4.81 11/11 50 01 cc d 61.7/10.4 92.2/24 .3 42.0/12.2 63/63 50 00 multiv (low swing mode) cc d 2.31/2.34 7.62/6.33 1 .26/1.67 6.5/4.4 30 11 (8) fast (12) n/a pad_i_hv (13) cc d 0.5/0.5 1.9/1.9 0.3/0.3 1.5/1.5 0.5 n/a pull_hv cc d na 6000 5000/5000 50 n/a 1. these are worst case values that are estimated from simula tion and not tested. the values in the table are simulated at v dd = 1.14 v to 1.32 v, v ddeh = 4.5 v to 5.5 v, t a = t l to t h 2. this parameter is supplied for reference and is not guaranteed by design and not tested. 3. delay and rise/fall are measured to 20% or 80% of the respective signal. 4. this parameter is guaranteed by characteri zation before qualification rather than 100% tested. 5. in high swing mode, high/low swing pad vol and voh values ar e the same as those of the slew controlled output pads 6. medium slew-rate controlled output buffer. contains an input buffer and weak pullup/pulldown. 7. output delay is shown in figure 9: pad output delay . add a maximum of one system clock to the output delay for delay with respect to system clock. 8. can be used on the tester. 9. this drive select value is not supported. if selected, it will be approximately equal to 11. 10. slow slew-rate controlled output buffer. c ontains an input buffer and weak pullup/pulldown. 11. selectable high/low swing io pad with selectable slew in high swing mode only. 12. fast pads are 3.3 v pads. 13. stand alone input buffer. also has weak pull-up/pull-down.
electrical characteristics spc564a74l7, spc564a80b4, spc564a80l7 112/157 doc id 15399 rev 9 table 36. pad ac specifications (v dde = 3.3 v) (1) pad type c output delay (ns) (2),(3) low-to-high / high- to-low rise/fall edge (ns) (3),(4) drive load (pf) src/dsc min max min max msb,lsb medium (5),(6),(7) cc d 5.8/4.4 18/17 2.7/2.1 10/10 50 11 (8) cc d 16/13 46/49 11.2/8.6 34/34 200 n/a 10 (9) cc d 14/16 37/45 6.5/6.7 19/19 50 01 cc d 27/27 69/82 15/13 43/43 200 cc d 83/86 200/210 38/38 86/86 50 00 cc d 113/109 270/285 53/46 120/120 200 slow (7),(10) cc d 9.2/6.9 27/28 5.5/4.1 20/20 50 11 cc d 30/23 81/87 21/16 63/63 200 n/a 10 (9) cc d 31/31 80/90 15.4/15.4 42/42 50 01 cc d 58/52 144/155 32/26 82/85 200 cc d 162/168 415/415 80/82 190/190 50 00 cc d 216/205 533/540 106/95 250/250 200 multiv (7),(11) (high swing mode) cc d 3.7/3.1 10/10 30 11 (8) cc d 46/49 37/37 200 n/a 10 (9) cc d 32 15/15 50 01 cc d 72 46/46 200 cc d 210 100/100 50 00 cc d 295 134/134 200 multiv (low swing mode) not a valid operational mode fast cc d 2.5/2.5 1.2/1.2 10 00 cc d 2.5/2.5 1.2/1.2 20 01 cc d 2.5/2.5 1.2/1.2 30 10 cc d 2.5/2.5 1.2/1.2 50 11 (8) pad_i_hv (12) cc d 0.5/0.5 3/3 0.4/0 .4 1.5/1.5 0.5 n/a pull_hv cc d na 6000 5000/5000 50 n/a 1. these are worst case values that are estimated from simula tion and not tested. the values in the table are simulated at v dd = 1.14 v to 1.32 v, v dde = 3 v to 3.6 v, v ddeh = 3 v to 3.6 v, t a = t l to t h . 2. this parameter is supplied for reference and is not guaranteed by design and not tested. 3. delay and rise/fall are measured to 20% or 80% of the respective signal.
spc564a74l7, spc564a80b4, spc564a80l7 electrical characteristics doc id 15399 rev 9 113/157 figure 9. pad output delay 4. this parameter is guaranteed by characteri zation before qualification rather than 100% tested. 5. in high swing mode, high/low swing pad vol and voh values ar e the same as those of the slew controlled output pads 6. medium slew-rate controlled output buffer. contains an input buffer and weak pullup/pulldown. 7. output delay is shown in figure 9 . add a maximum of one system clock to the out put delay for delay with respect to system clock. 8. can be used on the tester. 9. this drive select value is not supported. if selected, it will be approximately equal to 11. 10. slow slew-rate controlled output buffer. c ontains an input buffer and weak pullup/pulldown. 11. selectable high/low swing io pad with selectable slew in high swing mode only. 12. stand alone input buffer. also has weak pull-up/pull-down. vdde/2 v oh v ol rising edge output delay falling edge output delay pad data input pad output
electrical characteristics spc564a74l7, spc564a80b4, spc564a80l7 114/157 doc id 15399 rev 9 3.17 ac timing 3.17.1 reset and configuration pin timing figure 10. reset and configuration pin timing table 37. reset and configuration pin timing (1) # characteristic symbol min max unit 1 reset pulse width (2) t rpw 10 ? t cyc 2 reset glitch detect pulse width t gpw 2?t cyc 3 pllref, bootcfg, wkpcfg setup time to rstout valid t rcsu 10 ? t cyc 4 pllref, bootcfg, wkpcfg hold time to rstout valid t rch 0?t cyc 1. reset timing specified at: v ddeh = 3.0 v to 5.25 v, v dd = 1.14 v to 1.32 v, t a =t l to t h . 2. reset pulse width is measured from 50% of the falling edge to 50% of the rising edge. 1 2 reset rstout wkpcfg 3 4 bootcfg
spc564a74l7, spc564a80b4, spc564a80l7 electrical characteristics doc id 15399 rev 9 115/157 3.17.2 ieee 1149.1 interface timing note: the nexus/jtag read/write access control/status register (rwcs) write (to begin a read access) or the write to the read/write access data register (rwd) (to begin a write access) does not actually begin its action until 1 jtag clock (tck) after leaving the jtag update-dr state. this preven ts the access from being pe rformed and therefore will not signal its completion via the ready (rdy) output unless the jtag controller receives an additional tck. in addition, evti is not latched into the device unless there are clock transitions on tck. the tool/debugger must provide at least one tck clock for the evti signal to be recognized by the mcu. when using the rdy signal to indicate the end of a nexus read/write access, ensure that tck continues to run for at least 1 tck after leaving the update-dr state. this can be just a tck with tms low while in the run-test /idle state or by continuing with the table 38. jtag pin ac electrical characteristics (1) # symbol c characteristic min. value max. value unit 1t jcyc cc d tck cycle time 100 ? ns 2t jdc cc d tck clock pulse width 40 60 ns 3t tckrise cc d tck rise and fall times (40% - 70%) ?3ns 4t tmss, t tdis cc d tms, tdi data setup time 5 ? ns 5t tmsh, t tdih cc d tms, tdi data hold time 25 ? ns 6t tdov cc d tck low to tdo data valid ? 22 (2) ns 7t tdoi cc d tck low to tdo data invalid 0 ? ns 8t tdohz cc d tck low to tdo high impedance ? 22 ns 9t jcmppw cc d jcomp assertion time 100 ? ns 10 t jcmps cc d jcomp setup time to tck low 40 ? ns 11 t bsdv cc d tck falling edge to output valid ? 50 ns 12 t bsdvz cc d tck falling edge to output valid out of high impedance ?50ns 13 t bsdhz cc d tck falling edge to output high impedance ?50ns 14 t bsdst cc d boundary scan input valid to tck rising edge 25 (3) ?ns 15 t bsdht cc d tck rising edge to boundary scan input invalid 25 (3) ?ns 1. jtag timing specified at v dd = 1.14 v to 1.32 v, v ddeh = 4.5 v to 5.5 v with multi-voltage pads programmed to low- swing mode, t a = t l to t h, and c l = 30 pf with dsc = 0b10, src = 0b11. t hese specifications apply to jtag boundary scan only. see table 39 for functional specifications. 2. pad delay is 8?10 ns. remainder incl udes tck pad delay, clock tree delay logic delay and tdo output pad delay. 3. for 20 mhz tck.
electrical characteristics spc564a74l7, spc564a80b4, spc564a80l7 116/157 doc id 15399 rev 9 next nexus/jtag command. expect the affect of evti and rdy to be delayed by edges of tck. note: rdy is not available in all packages of all devices. figure 11. jtag test clock input timing figure 12. jtag test access port timing tck 1 2 2 3 3 tck 4 5 6 7 8 tms, tdi tdo
spc564a74l7, spc564a80b4, spc564a80l7 electrical characteristics doc id 15399 rev 9 117/157 figure 13. jtag jcomp timing tck jcomp 9 10
electrical characteristics spc564a74l7, spc564a80b4, spc564a80l7 118/157 doc id 15399 rev 9 figure 14. jtag boundary scan timing 3.17.3 nexus timing tck output signals input signals output signals 11 12 13 14 15 table 39. nexus debug port timing (1) # symbol c characteristic min. value max. value unit 1t mcyc cc d mcko cycle time 2 (2),(3) 8t cyc 1a t mcyc cc d absolute minimum mcko cycle time 25 (4) ?ns 2t mdc cc d mcko duty cycle 40 60 % 3t mdov cc d mcko low to mdo data valid (5) - 0.1 0.35 t mcyc 4t mseov cc d mcko low to mseo data valid (5) - 0.1 0.35 t mcyc 6t evtov cc d mcko low to evto data valid (5) - 0.1 0.35 t mcyc 7t evtipw cc d evti pulse width 4.0 ? t tcyc 8t evtopw cc d evto pulse width 1 ? t mcyc
spc564a74l7, spc564a80b4, spc564a80l7 electrical characteristics doc id 15399 rev 9 119/157 figure 15. nexus output timing 9t tcyc cc d tck cycle time 4 (6),(7) ?t cyc 9a t tcyc cc d absolute minimum tck cycle time 100 (8) ?ns 10 t tdc cc d tck duty cycle 40 60 % 11 t ntdis cc d tdi data setup time 5 ? ns 12 t ntdih cc d tdi data hold time 25 ? ns 13 t ntmss cc d tms data setup time 5 ? ns 14 t ntmsh cc d tms data hold time 25 ? ns 15 ? cc d tdo propagation delay from falling edge of tck ?19.5 ns 16 ? cc d tdo hold time with respect to tck falling edge (minimum tdo propagation delay) 5.25 ? ns 1. all nexus timing relative to mcko is measured from 50 % of mcko and 50% of the respective signal. nexus timing specified at v dd = 1.14 v to 1.32 v, v ddeh = 4.5 v to 5.5 v with multi-voltage pads programmed to low-swing mode, t a =t l to t h , and c l = 30 pf with dsc = 0b10. 2. achieving the absolute minimum mcko cy cle time may require setting the mcko di vider to more than its minimum setting (npc_pcr[mcko_div] depending on the ac tual system frequency being used. 3. this is a functionally allowable featur e. however, this may be limited by the ma ximum frequency specified by the absolute minimum mcko period specification. 4. this may require setting the mco divider to more t han its minimum setting (npc_pcr[mcko_div]) depending on the actual system frequency being used. 5. mdo, mseo , and evto data is held valid until next mcko low cycle. 6. achieving the absolute minimum tck cycl e time may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability of the design (system frequency / 4) depending on the actual system frequency being used. 7. this is a functionally allowable featur e. however, this may be limited by the ma ximum frequency specified by the absolute minimum tck period specification. 8. this may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability of the design (system frequency / 4) depending on the actual system frequency being used. table 39. nexus debug port timing (1) (continued) # symbol c characteristic min. value max. value unit 1 2 4 6 mcko mdo mseo evto output data valid 3
electrical characteristics spc564a74l7, spc564a80b4, spc564a80l7 120/157 doc id 15399 rev 9 figure 16. nexus event trigger and test clock timings figure 17. nexus tdi, tms, tdo timing tck 9 7 8 evti evto 8 7 tck 11 12 15 tms, tdi tdo 13 14 16
spc564a74l7, spc564a80b4, spc564a80l7 electrical characteristics doc id 15399 rev 9 121/157 n table 40. nexus debug port operating frequency package nexus width nexus routing nexus pin usage max. operating frequency mdo[0:3] mdo[4:11] cal_mdo[4:11] lqfp176 bga208 bga324 reduced port mode (1) route to mdo (2) nexus data out [0:3] gpio gpio 40 mhz (3) full port mode (4) route to mdo (2) nexus data out [0:3] nexus data out [4:11] gpio 40 mhz (5),(6) csp496 reduced port mode (1) route to mdo (2) nexus data out [0:3] gpio gpio 40 mhz (3) full port mode (4) route to mdo (2) nexus data out [0:3] nexus data out [4:11] gpio 40 mhz (5),(6) route to cal_mdo (7) cal nexus data out [0:3] gpio cal nexus data out [4:11] 40 mhz (3) 1. npc_pcr[fpm] = 0 2. npc_pcr[nexcfg] = 0 3. the nexus aux port runs up to 40 mhz. set npc_pcr[mcko _div] to divide-by-two if t he system frequency is greater than 40 mhz. 4. npc_pcr[fpm] = 1 5. set the npc_pcr[mcko_div] to divide by two if the syst em frequency is between 40 mhz and 80 mhz inclusive. set the npc_pcr[mcko_div] to divide by four if the system frequency is greater than 80 mhz. 6. pad restrictions limit the maximum o peration frequency in these configurations 7. npc_pcr[nexcfg] = 1
electrical characteristics spc564a74l7, spc564a80b4, spc564a80l7 122/157 doc id 15399 rev 9 3.17.4 external bus in terface (ebi) and calibrati on bus interface timing table 41. external bus interface maximum operating frequency port width multiplexed mode addr[12:15] pin usage addr[16:31] pin usage data[0:15] pin usage max. operating frequency 16-bit yes addr[12:15] gpio addr[16:31] data[0:15] 66 mhz (1) 16-bit no addr[12:15] addr[16:31] data[0:15] 33 mhz (2),(3) 32-bit yes addr[12:15] addr[16:31] data[16:31] data[0:15] 33 mhz (2),(3) 1. set siu_eccr[ebdf] to divide by two or divide by four if the system frequency is greater than 66 mhz. 2. system frequency must be ? 132 mhz and siu_eccr[ebdf] set to divide by four. 3. pad restrictions limit the maximum operating frequency. table 42. calibration bus interface maximum operating frequency port width multiplexed mode cal_addr[12:15] pin usage cal_addr[16:30] pin usage cal_data[0:15] pin usage max. operating frequency 16-bit yes gpio gpio cal_addr[12:30] cal_data[0:15] 66 mhz (1) 16-bit no cal_addr[12:15] cal_addr[ 16:30] cal_data[0:15] 66 mhz (1) 32-bit yes cal_we[2:3] cal_data[31] cal_addr[16:30] cal_data[16:30] cal_addr[0:15] cal_data[0:15] 66 mhz (1) 1. set siu_eccr[ebdf] to divide by two or divide by four if the system frequency is greater than 66 mhz table 43. external bus interface (ebi) and calibration bus operation timing (1) # symbol c characteristic 66 mhz (ext. bus) (2) unit notes min max 1t c cc p clkout period 15.2 ? ns signals are measured at 50% v dde . 2t cdc cc d clkout duty cycle 45% 55% t c 3t crt cc d clkout rise time ? (3) ns 4t cft cc d clkout fall time ? (3) ns 5t coh cc d clkout posedge to output signal invalid or high z(hold time) ? addr[8:31] ?cs[0:3] ? data[0:31] ?oe ? rd_wr ?ts ?we [0:3]/be [0:3] 1.3 ? ns
spc564a74l7, spc564a80b4, spc564a80l7 electrical characteristics doc id 15399 rev 9 123/157 figure 18. clkout timing 6t cov cc d clkout posedge to output signal valid (output delay) addr[8:31] cs[0:3] data[0:31] oe rd_wr ts we [0:3]/be [0:3] ?9ns 7t cis cc d input signal valid to clkout posedge (setup time) data[0:31] 6.0 ? ns 8t cih cc d clkout posedge to input signal invalid (hold time) data[0:31] 1.0 ? ns 9t apw cc d ale pulse width (4) 6.5 ? ns 10 t aai cc d ale negated to address invalid 4 1.5 (5) ?ns 1. external bus and calibrati on bus timing specified at f sys = 150 mhz and 100 mhz, v dd = 1.14 v to 1.32 v, v dde = 3 v to 3.6 v (unless stated otherwise), t a =t l to t h , and c l = 30 pf with dsc = 0b10. 2. the external bus is limited to half t he speed of the internal bus. the maximum ex ternal bus frequency is 66 mhz for 16-bit muxed mode and 33 mhz for non-muxed mode. for the ebi divisi on factor should be set acco rdingly based on the internal frequency being used. 3. refer to fast pad timing in table 35 and table 36 (different values for 1.8 v vs. 3.3 v). 4. measured at 50% of ale. 5. when cal_ts pad is used for cal_ale functi on the hold time is 1 ns instead of 1.5 ns. table 43. external bus interface (ebi) and calibration bus operation timing (1) (continued) # symbol c characteristic 66 mhz (ext. bus) (2) unit notes min max 1 2 2 3 4 clkout vdde/2 vol_f voh_f
electrical characteristics spc564a74l7, spc564a80b4, spc564a80l7 124/157 doc id 15399 rev 9 figure 19. synchronous output timing 6 5 5 clkout bus 5 output signal output vdde/2 vdde/2 vdde/2 vdde/2 6 5 output signal vdde/2 6
spc564a74l7, spc564a80b4, spc564a80l7 electrical characteristics doc id 15399 rev 9 125/157 figure 20. synchronous input timing figure 21. ale signal timing 7 8 clkout input bus 7 8 input signal vdde/2 vdde/2 vdde/2 system clock clkout ale ts addr data a/d 9 10
electrical characteristics spc564a74l7, spc564a80b4, spc564a80l7 126/157 doc id 15399 rev 9 3.17.5 external interr upt timing (irq pin) figure 22. external interrupt timing 3.17.6 etpu timing table 44. external interrupt timing (1) # characteristic symbol min max unit 1 irq pulse width low t ipwl 3?t cyc 2 irq pulse width high t ipwh 3?t cyc 3 irq edge to edge time (2) t icyc 6?t cyc 1. irq timing specified at v dd = 1.14 v to 1.32 v, v ddeh = 3.0 v to 5.5 v, v dd33 and v ddsyn = 3.0 v to 3.6 v, t a =t l to t h . 2. applies when irq pins are configured for rising edge or falling edge events, but not both. irq 1 2 3 table 45. etpu timing (1) # characteristic symbol min max unit 1 etpu input channel pulse width t icpw 4?t cyc 2 etpu output channel pulse width t ocpw 2 (2) ?t cyc 1. etpu timing specified at v dd = 1.08 v to 1.32 v, v ddeh = 3.0 v to 5.5 v, v dd33 and v ddsyn = 3.0 v to 3.6 v, t a =t l to t h , and c l = 200 pf with src = 0b00. 2. this specification does not include the ri se and fall times. when calculating the mi nimum etpu pulse widt h, include the rise and fall times defined in the slew rate control fiel ds (src) of the pad conf iguration registers (pcr).
spc564a74l7, spc564a80b4, spc564a80l7 electrical characteristics doc id 15399 rev 9 127/157 3.17.7 emios timing 3.17.8 dspi timing dspi channel frequency support for the spc564a80 mcu is shown in ta bl e 4 7 . timing specifications are in ta b l e 4 8 . table 46. emios timing (1) # symbol c characteristic min. value max. value unit 1t mipw cc d emios input pulse width 4 ? t cyc 2t mopw cc d emios output pulse width 1 ? t cyc 1. emios timing specified at f sys = 80 mhz, v dd = 1.14 v to 1.32 v, v ddeh = 4.5 v to 5.5 v, t a = t l to t h , and c l = 50 pf with src = 0b00. table 47. dspi channel frequency support system clock (mhz) dspi use mode max. usable frequency (mhz) notes 150 lvds 37.5 use sysclock /4 divide ratio. non-lvds 18.75 use sysclock /8 divide ratio. 120 lv d s 4 0 use sysclock /3 divide ratio. gives 33/66 duty cycle. use dspi configuration dbr=0b1 (double baud rate), br=0b0000 (scaler value 2) and pbr=0b01 (prescaler value 3). non-lvds 20 use sysclock /6 divide ratio. 80 lvds 40 use sysclock /2 divide ratio. non-lvds 20 use sysclock /4 divide ratio. table 48. dspi timing (1),(2) # symbol c characteristic c ondition min. max. unit 1t sck cc d sck cycle time (3),(4),(5) 24.4 ns 2.9 ms ? 2t csc cc d pcs to sck delay (6) 22 (7) ?ns 3t asc cc d after sck delay (8) 21 (9) ?ns 4t sdc cc d sck duty cycle ( ? t sc )?2 ( ? t sc )+2 ns 5t a cc d slave access time (ss active to sout driven) ?25ns 6t dis cc d slave sout disable time (ss inactive to sout high-z or invalid) ?25ns 7t pcsc cc d pcsx to pcss time 4 (10) ?ns 8t pasc cc d pcss to pcsx time 5 (11) ?ns
electrical characteristics spc564a74l7, spc564a80b4, spc564a80l7 128/157 doc id 15399 rev 9 9t sui cc data setup time for inputs d master (mtfe = 0) v ddeh =4.5?5.5 v 20 ? ns d v ddeh =3?3.6 v 23.5 ? dslave 2? d master (mtfe = 1, cpha = 0) (12) 8? d master (mtfe = 1, cpha = 1) v ddeh =4.5?5.5 v 20 ? d v ddeh =3?3.6 v 23.5 ? 10 t hi cc data hold time for inputs d master (mtfe = 0) -4 ? ns dslave 7 ? d master (mtfe = 1, cpha = 0) (12) 21 ? d master (mtfe = 1, cpha = 1) -4 ? 11 t suo cc data valid (after sck edge) d master (mtfe = 0) v ddeh =4.5?5.5 v ? 5 ns d v ddeh =3?3.6 v ? 6.3 d slave v ddeh =4.5?5.5 v ? 25 d v ddeh =3?3.6 v ? 27 d master (mtfe = 1, cpha = 0) ? 21 d master (mtfe = 1, cpha = 1) v ddeh =4.5?5.5 v ? 5 d v ddeh =3?3.6 v ? 6.3 12 t ho cc data hold time for outputs d master (mtfe = 0) v ddeh =4.5?5.5 v ?5 ? ns d v ddeh =3 ?3.6 v ?7.5 ? dslave 5.5 ? d master (mtfe = 1, cpha = 0) 3 ? d master (mtfe = 1, cpha = 1) v ddeh =4.5?5.5 v ?5 ? d v ddeh =3?3.6 v ?7.5 ? 1. all dspi timing specifications use the fastest slew rate (src = 0b11) on me dium-speed pads. dspi signals using slow pads have an additional delay based on the slew rate. dspi timing is specified at v ddeh = 3to3.6v and v ddeh = 4.5 to 5.5 v, t a =t l to t h , and c l = 50 pf with src = 0b11. 2. data is verified at f sys = 102 mhz and 153 mhz (100 mhz and 150 mhz + 2% frequency modulation). table 48. dspi timing (1),(2) (continued) # symbol c characteristic c ondition min. max. unit
spc564a74l7, spc564a80b4, spc564a80l7 electrical characteristics doc id 15399 rev 9 129/157 figure 23. dspi classic spi timing ? master, cpha = 0 3. the minimum dspi cycle time restricts the baud rate sele ction for given system clock ra te. these numbers are calculated based on two spc564a80 devices comm unicating over a dspi link. 4. the actual minimum sck cycle ti me is limited by pad performance. 5. for dspi channels using lvds output operation, up to 40 mhz sck cycle time is supported. for non-lvds output, maximum sck frequency is 20 mhz. appr opriate clock division must be applied. 6. the maximum value is programmable in dspi_ctarx[pssck] and dspi_ctarx[cssck]. 7. timing met when pcssck = 3(01), and cssck =2 (0000). 8. the maximum value is programmable in dspi_ctarx[pasc] and dspi_ctarx[asc]. 9. timing met when asc = 2 (0000), and pasc = 3 (01). 10. timing met when pcssck = 3. 11. timing met when asc = 3. 12. this number is calculated assuming the smpl_pt bitfield in dspi_mcr is set to 0b10. data last data first data first data data last data sin sout pcsx sck output 4 9 12 1 11 10 4 sck output (cpol=0) (cpol=1) 3 2 note: refer to table 48 for the numbers.
electrical characteristics spc564a74l7, spc564a80b4, spc564a80l7 130/157 doc id 15399 rev 9 figure 24. dspi classic spi timing ? master, cpha = 1 data last data first data sin sout 12 11 10 last data data first data sck output sck output pcsx 9 (cpol=0) (cpol=1) note: refer to table 48 for the numbers. last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 12 sck input first data last data sck input 2 (cpol=0) (cpol=1) note: refer to table 48 for the numbers.
spc564a74l7, spc564a80b4, spc564a80l7 electrical characteristics doc id 15399 rev 9 131/157 figure 25. dspi classic spi timing ? slave, cpha = 0 figure 26. dspi classic spi timing ? slave, cpha = 1 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol=0) (cpol=1) note: refer to table 48 for the numbers. pcsx 3 1 4 10 4 9 12 11 sck output sck output sin sout first data data last data first data data last data 2 (cpol=0) (cpol=1) note: refer to table 48 for the numbers.
electrical characteristics spc564a74l7, spc564a80b4, spc564a80l7 132/157 doc id 15399 rev 9 figure 27. dspi modified transfer format timing ? master, cpha = 0 figure 28. dspi modified transfer format timing ? master, cpha = 1 pcsx 10 9 12 11 sck output sck output sin sout first data data last data first data data last data (cpol=0) (cpol=1) note: refer to table 48 for the numbers.
spc564a74l7, spc564a80b4, spc564a80l7 electrical characteristics doc id 15399 rev 9 133/157 figure 29. dspi modified transfer format timing ? slave, cpha =0 last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 sck input first data last data sck input 2 (cpol=0) (cpol=1) 12 note: refer to table 48 for the numbers.
electrical characteristics spc564a74l7, spc564a80b4, spc564a80l7 134/157 doc id 15399 rev 9 figure 30. dspi modified transfer format timing ? slave, cpha =1 figure 31. dspi pcs strobe (pcss ) timing 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol=0) (cpol=1) note: refer to table 48 for the numbers. pcsx 7 8 pcss note: refer to table 48 for the numbers.
spc564a74l7, spc564a80b4, spc564a80l7 electrical characteristics doc id 15399 rev 9 135/157 3.17.9 eqadc ssi timing figure 32. eqadc ssi timing table 49. eqadc ssi timing characteristics (pads at 3.3 v or at 5.0 v) (1) cload = 25 pf on all outputs. pad drive strength set to maximum. # symbol c rating min typ max unit 1f fck cc d fck frequency (2), (3) 1/17 1 ? 2f sys_clk 1t fck cc d fck period (t fck = 1/ f fck ) 2 17 t sys_clk 2t fckht cc d clock (fck) high time t sys_clk ? 6.5 9* t sys_clk ? 6.5 ns 3t fcklt cc d clock (fck) low time t sys_clk ? 6.5 8* t sys_clk ? 6.5 ns 4t sds_ll cc d sds lead/lag time -7.5 7.5 ns 5t sdo_ll cc d sdo lead/lag time -7.5 7.5 ns 6t dvfe cc d data valid from fck falling edge (t fcklt+ t sdo_ll ) 1ns 7t eq _ su cc d eqadc data setup time (inputs) 22 ns 8t eq_ho cc d eqadc data hold time (inputs) 1 ns 1. ss timing specified at f sys = 80 mhz, v dd = 1.14 v to 1.32 v, v ddeh = 4.5 v to 5.5 v, t a = t l to t h , and c l = 50 pf with src = 0b00. 2. maximum operating frequency is highly dependent on track delays, master pad dela ys, and slave pad delays. 3. fck duty is not 50% when it is generated through th e division of the system clock by an odd number. 1st (msb) 2nd 25th 26th 1st (msb) 2nd 25th 26th 8 7 5 6 5 4 4 3 1 3 2 1 2 fck sds sdo external device data sample at sdi eqadc data sample at fck falling edge fck rising edge
electrical characteristics spc564a74l7, spc564a80b4, spc564a80l7 136/157 doc id 15399 rev 9 3.17.10 flexcan system clock source table 50. flexcan engine system clock divide r threshold # symbol characteristic value unit 1f can_th flexcan engine system clock threshold 100 mhz table 51. flexcan engine system clock divider system frequency required siu_sysdiv[can_src] value <= f can_th 0 (1),(2) 1. divides system clock sour ce for flexcan engine by 1. 2. system clock is only selected fo r flexcan when can_cr[clk_src] = 1. > f can_th 1 (2),(3) 3. divides system clock sour ce for flexcan engine by 2.
spc564a74l7, spc564a80b4, spc564a80l7 packages doc id 15399 rev 9 137/157 4 packages 4.1 ecopack ? in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
packages spc564a74l7, spc564a80b4, spc564a80l7 138/157 doc id 15399 rev 9 4.2 package mechanical data 4.2.1 lqfp176
spc564a74l7, spc564a80b4, spc564a80l7 packages doc id 15399 rev 9 139/157 figure 33. lqfp176 package mechanical drawing
packages spc564a74l7, spc564a80b4, spc564a80l7 140/157 doc id 15399 rev 9 table 52. lqfp176 package mechanical data ref. databook millimeters (1) 1. controlling dimension: millimeter inches typ min max typ min max typ min max a 1.600 0.063 a1 0.050 0.150 0.002 a2 1.350 1.450 0.053 0.057 b 0.170 0.270 0.007 0.011 c 0.090 0.200 0.004 0.008 d 23.900 24.100 0.941 0.949 e 23.900 24.100 0.941 0.949 e 0.500 0.020 hd 25.900 26.100 1.020 1.028 he 25.900 26.100 1.020 1.028 l (2) 2. l dimension is measured at gauge pl ane at 0.25 above the seating plane. 0.450 0.750 0.018 0.030 l1 1.000 0.039 zd 1.250 0.049 ze 1.250 0.049 ccc 0.080 0.003 angle 0 o 7 o 07 o
spc564a74l7, spc564a80b4, spc564a80l7 packages doc id 15399 rev 9 141/157 4.2.2 bga208 1. the terminal a1 corner must be identified on the top surface by using a corner chamfer, ink or metallized markings, or other feature of package body or integral heatslug. a distinguishing feature is allowable on the bottom su rface of the package to identify the terminal a1 corner. exact shape of each corner is optional. table 53. lbga208 mechanical data symbol mm inches (1) min typ max min typ max a (2) 1.70 0.0669 a1 0.30 0.0118 a2 1.085 0.0427 a3 0.30 0.0118 a4 0.80 0.0315 b (3) 0.50 0.60 0.70 0.0197 0.0236 0.0276 1 3 5 7 9 111315 2 4 6 8 10 12 14 16 r l k t j n m p a b h g f d c e a1 corner index area (see note 1) bottom view b (208 balls) m m eee fff cab c seating plane a d d1 f e e1 f e a a1 a2 a3 a4 d ddd e b a c
packages spc564a74l7, spc564a80b4, spc564a80l7 142/157 doc id 15399 rev 9 4.2.3 pbga324 d 16.80 17.00 17.20 0.6614 0.6693 0.6772 d1 15.00 0.5906 e 16.80 17.00 17.20 0.6614 0.6693 0.6772 e1 15.00 0.5906 e 1.00 0.0394 f 1.00 0.0394 ddd 0.20 0.0079 eee (4) 0.25 0.0098 fff (5) 0.10 0.0039 1. values in inches are converted from mm and rounded to 4 decimal digits. 2. lbga stands for l ow profile b all g rid a rray. ?low profile: the total profile height (dim a) is measured from the seating plane to the top of the component ?the maximum total package height is calculated by the following methodology: a2 typ+a1 typ + ? (a1 2 +a3 2 +a4 2 tolerance values) ? low profile: 1.20mm < a < 1.70mm 3. the typical ball diameter before mounting is 0.60mm. 4. the tolerance of position that controls the location of the pattern of balls with respect to datums a and b. for each ball there is a cylindric al tolerance zone eee perpendicular to datum c and located on true position with respect to datums a and b as defined by e. the axis perpendicular to datum c of each ball must lie within this tolerance zone. 5. the tolerance of position that controls the location of the balls within the matrix with respect to each other. for each ball there is a cylindrical tolerance zone fff perpendicular to datum c and located on true position as defined by e. the axis perpendicul ar to datum c of each ball must lie within this tolerance zone. each tolerance zone fff in the array is cont ained entirely in the respective zone eee above. the axis of each ball must lie simu ltaneously in both tolerance zones. table 53. lbga208 mechanical data (continued) symbol mm inches (1) min typ max min typ max
spc564a74l7, spc564a80b4, spc564a80l7 packages doc id 15399 rev 9 143/157 figure 34. pbga324 package mechanical drawing
packages spc564a74l7, spc564a80b4, spc564a80l7 144/157 doc id 15399 rev 9 table 54. pbga324 package mechanical data symbol mm inches min. typ. max. min. typ. max. a (1),(2),(3) 1. max mounted height is 1.77mm.based on 0.35mm ball pad diameter. solder paste is 0.15mm thickness and 0.35mm diameter. 2. pbga stands for plasti c ball grid array. 3. the terminal a1 corner must be identified on the top surface by using a corner chamfer, ink or metallized markings, or other feature of package body or integral heatslug. a distinguishing feature is allowable on the bottom surface of the package to identify the termi nal a1corner. exact shape of each corner is optional. 1.720 1.620 1.720 1.820 a1 0.270 0.350 0.400 0.450 a2 1.320 1.320 b 0.550 0.6000 0.650 0.550 0.600 0.650 d 22.80 23.00 23.200 22.900 23.000 23.100 d1 21.00 21.000 e 22.800 23.000 23.200 22.900 23.000 23.100 e1 21.000 21.000 e 0.950 1.000 1.050 0.950 1.000 1.050 f 0.875 1.000 1.125 0.875 1.000 1.125 ddd 0.200 0.200
spc564a74l7, spc564a80b4, spc564a80l7 ordering information doc id 15399 rev 9 145/157 5 ordering information ta bl e 5 5 shows the orderable part numbers for the spc564a80 series. table 55. order codes order code flash/sram package speed (mhz) spc564a74l7cfa 3 mb/160 kb 176lqfp 150 spc564a74b2cfa 3 mb/160 kb 208lbga 150 spc564a74b4cfa 3 mb/160 kb 324pbga 150 spc564a80l7cfc 4 mb/192 kb lqfp176 80 spc564a80b2cfc 4 mb/192 kb lbga208 80 spc564a80b4cfc 4 mb/192 kb pbga324 80 spc564a80l7cfb 4 mb/192 kb lqfp176 120 spc564a80b2cfb 4 mb/192 kb lbga208 120 spc564a80b4cfb 4 mb/192 kb pbga324 120 spc564a80l7cfa 4 mb/192 kb lqfp176 150 spc564a80b2cfa 4 mb/192 kb lbga208 150 spc564a80b4cfa 4 mb/192 kb pbga324 150 spc564a80h1efa 4 mb/192 kb kgd 150
ordering information spc564a74l7, spc564a80b4, spc564a80l7 146/157 doc id 15399 rev 9 figure 35. product code structure memory conditioning core family y = tray r = tape and reel a = 150 mhz b = 120 mhz c = 80 mhz f = optional flexray controller b = ?40 to 105 c c = ?40 to 125 c b2 = lbga208 b4 = pbga324 l7 = lqfp176 h1 = known good die 80 = 4 mb 74 = 3 mb a = spc564a80 family 4 = e200z4 spc56 = power architecture in 90 nm temperature package custom vers. spc56 80 y 4a c l5 f example code: product identifier max freq. a
spc564a74l7, spc564a80b4, spc564a80l7 document revision history doc id 15399 rev 9 147/157 6 document revision history table 56. revision history date revision changes 23-feb-2009 1 initial release 09-dec-2009 2 maximum device speed is 145 mhz (was 150 mhz) 16-entry memory protection unit (mpu). was incorrectly listed as 8-entry. 288-ball bga package deleted feature details section added changes to signal summary table: ? added any function to an[10] ? added anw function to an[8] changes to 208 ball bga ballmap: ? a12 is an12-sds (was an12) ? a15 is vrc33 (was vdd33) ? b12 is an13-sdo (was an13) ? c12 is an14sdi (was an14) ? c13 is an15-fck (was an15) ? d1 is vrc33 (was vdd33) ? f13 is vddeh6ab (was vddeh6) ? h13 is gpio99 (was pcsa3) ? j15 is gpio98 (was pcsa2) ? k4 is now vddeh1ab (was vddeh1) ? n6 is now vrc33 (was vdd33) ? n9 is vddeh4ab (was vddeh4) ? n12 is now vrc33 (was vdd33) ? p6 is now nc ? t13 is vdde5 (was nc) changes to 324 ball bga ballmap: ? a6 is vdda (was vdda1) ? a7 is vssa (was vssa1) ? a15 is vssa (was vssa0) ? a16 is an12_sds (was an12) ? a17 is mdo11_etpua29o (was mdo11) ? a18 is mdo10_etpua27o (was mdo10) ? a19 is mdo8_etpua21o (was mdo8) ? a21 is vrc33 (was vdd33) ? b1 is vrc33 (was vdd33) ? b15 is vssa (was vssa0) ? b16 is an13_sdo (was an13) ? b17 is mdo9_etpua25o (was mdo9) ? b18 is mdo7_etpua19o (was mdo7) ? b19 is mdo4_etpua2o (was mdo4) ? b22 is nic (was vdde7)
document revision history spc564a74l7, spc564a80b4, spc564a80l7 148/157 doc id 15399 rev 9 09-dec-2009 2 ? c4 is vdd (was vddeh1a) ? c15 is vdda (was vdda0) ? c16 is an14_sdi (was an14) ? c17 is mdo5_etpua4o (was mdo5) ? c21 is nic1 (was vdde7) ? d15 is vddeh7 (was vddeh9) ? d16 is an15_fck (was an15) ? d17 is mdo6_etpua13o (was mdo6) ? d20 is nic (was vdde7) ? e19 is nic (was vdde7) ? e22 is nic (was nc) ? f19 is nic (was vdde7) ? h4 is vddeh1ab (was vddeh1a) ? h19 is vddeh6ab (was vddeh10) ? j14 is nic (was vdde7) ? k19 is gpio99 (was pcsa3) ? m9 is vdde2 (was vdd2) ? m21 is gpio98 (was pcsa2) ? m22 is vddreg (was nc) ? n22 is nic (was nc) ? p2 is addr17 (was add17) ? p4 is vrc33 (was vdd33) ? r3 is vdde-eh (was vdde2) ? t21 is vss (was vrcvss) ? t22 is vss (was vsspll) ? u19 is vddeh6ab (was vddeh6a) ? w2 is vdde-eh (was vdde2) ? w7 is vrc33 (was vdd33) ? w14 is vddeh4ab (was vddeh4b) ? w21 is nic (was vrc33) ? y22 is vrc33 (was vdd33) ? ab22 is vss (was vsspll) recommended operating characteristics for power transistor updated pad current specifications updated lvds pad specifications updated. src does not apply to common mode voltage. temperature sensor electrical characteristics added eqadc electrical characteristics updated with vga gain specs pad ac specifications updated definition for rdy signal added to signal details v stby maximum is 5.5 v (was listed incorrectly as 6.0 v) i maxa maximum is 5 ma (was tbd) analog differential input functions added to an0?an7 in signal summary table 56. revision history (continued) date revision changes
spc564a74l7, spc564a80b4, spc564a80l7 document revision history doc id 15399 rev 9 149/157 02-apr-2010 3 internal release. changes to signal properties table (changes apply to revision 2 and later devices: ebi changes: ? we_be[2] (a2) and cal_we_be[2] (a3) signals added to cs[2] (pcr 2) ? we_be[3] (a2) and cal_we_be[3] (a3) signals added to cs[3] (pcr 3) calibration bus changes: ? cal_we[2]/be[2] (a2) signal added to cal_cs[2] (pcr 338) ? cal_we[3]/be[3] (a2) signal added to cal_cs[3] (pcr 339) ? cal_ale (a1) added to cal_addr[15] (pcr 340) eqadc changes: ? an[8] and an[38] pins swapped. an[8] is now on pins 9 (176-pin), b3 (208-ball) and d6 (324-ball). an[8] was on c5 (324-ball) on previous devices. an[38] is now on c5 (324-ball). an[38] was on pins 9 (176-p in), b3 (208-ball) and d6 (324-ball) on previous devices. ? anz function added to an11 pin reaction channels added to etpu2: ? rch0_a (a3) added to etpu_a[14] (pcr 128) ? rch0_b (a2) added to etpu_a[20] (pcr 134) ? rch0_c (a2) added to etpu_a[21] (pcr 135) ? rch1_a (a2) added to etpu_a[15] (pcr 129) ? rch1_b (a2) added to etpu_a[9] (pcr 123) ? rch1_c (a2) added to etpu_a[10] (pcr 124) ? rch2_a (a2) added to etpu_a[16] (pcr 130) ? rch3_a (a2) added to etpu_a[17] (pcr 131 ? rch4_a (a2) added to etpu_a[18] (pcr 132)) ? rch4_b (a2) added to etpu_a[11] (pcr 125) ? rch4_c (a2) added to etpu_a[12] (pcr 126) ? rch5_a (a2) added to etpu_a[19] (pcr 133) ? rch5_b (a2) added to etpu_a[28] (pcr 142) ? rch5_c (a2) added to etpu_a[29] (pcr 143) reaction channels added to emios: ? rch2_b (a2) added to emios[2] (pcr 181) ? rch2_c (a2) added to emios[4] (pcr 183) ? rch3_b (a2) added to emios[10] (pcr 189) ? rch3_c (a2) added to emios[11] (pcr 190) pad changes: ? etpua16 (pcr 130) has medium (was slow) pad ? etpua17 (pcr 131) has medium (was slow) pad ? etpua18 (pcr 132) has medium (was slow) pad ? etpua19 (pcr 133) has medium (was slow) pad ? etpua25 (pcr 139) has slow+lvds (was medium+lvds) pads table 56. revision history (continued) date revision changes
document revision history spc564a74l7, spc564a80b4, spc564a80l7 150/157 doc id 15399 rev 9 02-apr-2010 (cont) 3 (cont) signal details table updated: ? added etpu2 reaction channels ? changed irq[0:15] to two ranges, excludi ng irq6, which does not exist on this device ? changed tcr_a to tcrclka (tcr_a is the pin name, not the signal name) ? changed we_be[0:1] to we _be[0:3] (2 new signals added to rev. 2). also changed notation from ?we_be[n]? to ?we[n]/be[n]? to be consistent. changes to power/ground segmentation table: ? addr[20:21] removed from vdde2 segment; they are in vdde-eh ? cal_cs1 removed from vdde12 segment (there is no cal_cs1 on this device) ? cal_evto and cal_mcko removed from vdde12 segment. those pins do not exist ? vdde-vddeh renamed to vdde-eh ? emios24 removed from vddeh segment. that pin does not exist. ? etpua[0:9] added to vddeh4 segment ? renamed tcr_a in vddeh4 segment to tcrclka. ? extal and xtal added to vddeh6 segment ? an15-fck added to vddeh7 segment ? gpio98, gpio99, gpio206, gpio207 an d gpio219 added to vddeh7 segment. ? mseo1 added to vddeh7 segment ? power segment vddeh1a renamed to vddeh1 changes to 176-pin package pinout: ? changed pin 9 from an38 to an8. ? added note that pin 96 (vss) should be tied low. changes to 208-ball package ballmap: ? changed ball b3 from an38 to an8. ? added note that ball n13 (vss) should be tied low. 324-ball package ballmap updated for rev. 2 silicon ? renamed vdda (a6) to vdda0 ? renamed vssa (a7) to vssa0 ? an8 was on ball c5; it is now on d6 ? an38 was on ball d6; it is now on c5 ? renamed vssa (a15) to vssa1 ? renamed vdda (c15) to vdda1 ? rename vssa (b15) to vssa1 bga288 package is no longer offered changes to features list: ? correction: there are 6 reaction channels (was noted as 5) ? development trigger semaphore (dts) added to features list and feature details ? flexray module now has 128 message buffers (was 64) and ecc support added note after jtag pin ac electrical characteristics table detailing jtag evti and rdy signal clocking with tck. this affects debuggers. table 56. revision history (continued) date revision changes
spc564a74l7, spc564a80b4, spc564a80l7 document revision history doc id 15399 rev 9 151/157 02-apr-2010 (cont) 3 (cont) added information to ac timings section: ? new section added: reset and configuration pin timing ? new section added: external interrupt timing (irq pin) ? new section added: etpu timing ? added nexus debug port operating frequency table to nexus timings section ? added external bus interface maximum operating frequency table and calibration bus interface maximum operation frequency table ? added flexcan system clock source section changes to power management control (pmc) and power on reset (por) electrical specifications: ? max value for parameter 2 (vddreg) is 5.25 v (was 5.5 v) updated ?core voltage regulator controller external components preferred configuration? diagram. changes to dc electrical specifications table: ? slew rate on power supply pins (system requirement) changed to 25 v/ms (was 50 v/ms) throughout the document the maximum frequency is now 150 mhz (was 145 mhz) changes to dc electrical specifications: ? parameter classifications added ?v ddreg max value changed to 5.25 v (was 5.5 v) ?v oh_ls min value changed to 2.0 v (was 2.7 v) with a load current of 0.5 ma ?v ol_ls max value changed to 0.6 v (was 0.2*v ddeh ) with load current of 2 ma ?v indc min value changed to v ssa -0.3 (was v ssa -1.0) ?v indc max value changed to v dda +0.3 (was v dda +1.0) added new section: config uring sram wait states ? vrcctl external circuit updated. 01-oct-2010 4 updates to nexus timings: ?t mdov max value changed to 0.35 (was 0.2) ?t mseov max value changed to 0.35 (was 0.2) ?t evtov max value changed to 0.35 (was 0.2) updates to dc electrical specifications: ?v stby min value changed to 0.95 v (was 0.9 v) ?v stby has two ranges?for regulated mode and unregulated mode correction to pllmrfm elec trical specifications: ?v ddpll range is from 1.08 v to 3.6 v (was 3.0 v to 3.6 v. updates to pad ac specifications: ? specs with drive load = 200 pf deleted. dsc (drive strength control) values range from 10?50pf. ? i/o pad average i dde specifications updated (fast pad specs only) ? i/o pad v rc33 average i dde specifications (fast pad specs only) updates to reset and configuration pin timings: ? footnote added: reset pulse width is measured from 50% of the falling edge to 50% of the rising edge. ? timings are specified at v dd = 1.14 v to 1.32 v (was 1.08 v to 1.32 v). table 56. revision history (continued) date revision changes
document revision history spc564a74l7, spc564a80b4, spc564a80l7 152/157 doc id 15399 rev 9 01-oct-2010 (cont) 4 (cont) updates to ebi timings: ? note added to t aai : when cal_ts is used as cal_a le the hold time is 1 ns instead of 1.5 ns. ? correction: maximum calibration bus interface operating frequency is 66 mhz for all port configurations. ? vdde range in footnote 1 corrected to re ad, ?external bus and calibration bus timing specified at f sys = 150 mhz and 100 mhz, vdd = 1.14 v to 1.32 v, vdde = 3 v to 3.6 v (unles s stated otherwise)? (vdde range was 1.62 v to 3.6 v) correction to ieee 1149.1 timings: ? src value in footnote 1 corrected to read , ?jtag timing specified at vdd = 1.14 v to 1.32 v, vddeh = 4.5 v to 5.5 v with multi-voltage pads programmed to low- swing mode, ta = tl to th, and cl = 30 pf with dsc = 0b10, src = 0b11.? (src value was 0b00) correction to external interrupt timing (irq pin) timings: ? timings are specified at v dd = 1.14 v to 1.32 v (was 1.08 v to 1.32 v). update to dspi timings: ? some of the timing parameters ca n vary depending on the value of v dde . for these parameters, ranges are now defined for two ranges of v dde . change in signal name notation for dspi, can and sci signals: ? dspi: pcs_x[n] is now dspi_x_pcs[n] sout_x is now dspi_x_sout sin_x is now dspi_x_sin sck_x is now dspi_x_sck ?can: cntxx is now can_x_tx cnrxx is now can_x_rx ?sci: rxdx is now sci_x_rx txdx is now sci_x_tx updates to dc electrical specifications: ? slew rate on power supply pins specif ication changed to 25 v/ms (was 50 v/ms) v oh_ls min spec changed to 2.0 v at 0.5 ma (was 2.7 v at 0.5 ma) updated i/o pad current specifications updated i/o pad v rc33 current specifications corrections to nexus timing: ? maximum nexus debug port operating frequency is 40 mhz in all configurations ? to route nexus to mdo, clear npc_pcr[nexcfg] (formerly this was documented as npc_pcr[cal] ? to route nexus to cal_mdo, set npc_pcr[nexcfg]=1 (formerly this was documented as npc_pcr[cal] 10-feb-2011 5 ? minor editorial updates. ? re-organized the first few subsections of the ?overview? section. ? added ecsm to the block diagram. ? added information on the reacm, siu, and ecs modules to the ?block summary? section. table 56. revision history (continued) date revision changes
spc564a74l7, spc564a80b4, spc564a80l7 document revision history doc id 15399 rev 9 153/157 10-feb-2011 (cont) 5 (cont) ? added data[0:15] to v dde5 in the ?signal properties? table. ? updated vstby parameters in the ?power/ground segmentation? table. ? updated the parameter symbols and classifications throughout the document. ? updated footnote instances in the ?absolute maximum ratings? table. ? removed i maxa footnote in the ?absolute maximum ratings? table. ? updated the format of the ?e mi (electromagnetic interference) characteristics? table. ? removed the footnote on v ddreg in the ?power management control (pmc) and power on reset (por) electrical specifications? table. ? updated values for vbg, idd3p3, por3.3v_r, por3.3v_f, por5v_r, and por5v_f in the ?pmc electrical characteristics? table. ? updated ?bandgap reference supply voltage variation? in the ?pmc electrical characteristics? table. ? removed the ?vrc electrical specificat ions? table as it contained redundant information. ? updated vce sat and v be in the ?recommended power transistors? operating characteristics? table. ? updated v ih_ls in the ?dc electrical specifications? table. ? updated the v oh_ls min value in the ?dc electrical specifications? table. ? updated i ddstby and i ddstby150 in the ?dc electrical specifications? table. ? updated the i dda /i ref /i ddreg max value in the ?dc electrical specifications? table. ? updated i act_f , i act_mv_pu , i act_mv_pd , r pupd5k , r pupdmtch , and footnotes in the ?dc electrical specifications? table. ? updated medium pad type i dd33 values in the ?i/o pad v rc33 average i dde specifications? table. ? updated values for v od in the ?dspi lvds pad specification? table. ? removed the footnotes from the ?dspi lvds pad specifications? table. ? removed the redundant ?xtal load capaci tance? parameter instance from the ?pllmrfm electrical specifications? table. ? updated footnotes in the ?pllmrfm electrical specifications? table. ? updated values for offnc and gainnc in the ?eqadc conversion specifications (operating)? table. ? added diff max , diff max2 , diff max4 , and diff cmv parameters to the ?eqadc conversion specifications (operating)? table. ? added the maximum operating frequency values in the ?cutoff frequency for additional sram wait state? table. ? updated multiple entries in the ?apc, rwsc, wwsc settings vs. frequency of operation? table. ? removed footnote in the ?apc, rwsc, wwsc settings vs. frequency of operation? table. ? updated the typical values for t dwprogram ,, t pprogram , and t 16kpperase , and updated the initial max values for t 128kpperase and t 256kpperase in the ?flash program and erase specifications? table. ? changed the voltage in the ?pad ac specif ications? table title from 4.5 v to 5.0 v. ? added the maximum lh/hl output delay values for pad type multiv in the ?pad ac specifications (v dde = 3.3 v)? table. table 56. revision history (continued) date revision changes
document revision history spc564a74l7, spc564a80b4, spc564a80l7 154/157 doc id 15399 rev 9 03-feb-2012 6 ? minor editorial changes. ?in section 1.4: spc564a80 feature list , moved ?24 unified channels? after ?1 x emios?. ?in ta b l e 4 updated the following rows: dspi_d_sck /gpio [98] -changed ?-? to cs[2] dspi_d_sin /gpio[99] -changed ?-? to cs[3]. ?in ta b l e 1 2 column ?value? added conditional text. ?in ta b l e 2 1 made the following changes: -for the value ?vol_s? parameter changed from ?slow/ medium/multi-voltage pad i/o output low voltage? to ?slow/m edium pad i/o output low voltage?. -added a new row for ?iddstby27?. -for row ?iddstby(operating current 0.95 -1.2v)? added max value ?100? and changed typ value from ?125? to ?35?. -for row ?i ddstby (operating current 2 - 5.5v)? added max value ?110? and changed typ value from ?135? to ?45?. -for symbol ?i ddstby 150 (operating current 0.95 -1.2v)? added max value ?2000?, changed typ value from ?1050? to ?790?,c cell changed from ?t? to ?p? and for symbol ?i ddstby (operating current 2 - 5.5v)? added max value ?2000?, changed typ value from ?1050? to ?760?, c cell changed from ?t? to ?p?. -removed note 9 and note 10 (characterization based capability) from symbol ?v ol_hs ? . ? splitted table 28: eqadc conversion specifications (operating) into ta b l e 2 9 : eqadc single ended conversion specifications (operating) and table 30: eqadc differential ended conversion specifications (operating) ?in table 30: eqadc differential ended conversion specifications (operating) made the following changes: -added the note of diff cmv on all of the diff specs. -min value changed from (vrh-vrl)/2-5% to (vrh+vrl)/2-5 % and max value changed from (vrh-vrl)/2+5% to (vrh+vrl)/2+5%for diffcmv. ?in table 31: cutoff frequency for additional sram wait state made the following changes: -added note ?max frequencies including 2% pll fm?. -max operating frequency changed from ?96? to ?98? and ?150? to ?153?. ?in section 3.13: configur ing sram wait states , changed text from ?spc564a80 4m microcontroller reference manual ? to ?device reference manual?. ?in table 32: apc, rwsc, wwsc settings vs. frequency of operation , - added note for ?max flash operating frequency(mhz). - changed values from 30, 60,120, 150 to 20,61,123, 153 respectively in max flash operating frequency (mhz). ?in table 33: flash program and erase specifications , added two parameter ?t psrt ? and ?t esrt ?. ?in table 41: external bus interface maximum operating frequency , replacedthe <= symbol in notes with ?? ? added note ?refer to table dspi timing fo r the numbers? in all the figures under section 3.17.8: dspi timing . table 56. revision history (continued) date revision changes
spc564a74l7, spc564a80b4, spc564a80l7 document revision history doc id 15399 rev 9 155/157 03-feb-2012 (cont) 6 (cont) ? added table 17: spc564a80 external network specification . ? updated figure 8: core voltage regulator controller external components preferred configuration . ? changed external network parameter ce min value to ?3*2.35 f+5 f? from ?2*2.35 f+5 f? in table 17: spc564a80 external network specification . ? changed trans. line (differentia l zo) unit to from w in table 25: dspi lvds pad specification . 07-mar-2012 7 ? update table footnotes in table 21: dc electrical specifications . 21-mar-2012 8 ? minor editorial changes. ?in section 1.4, ?spc564a80 feature list , moved ?24 unified channels? after ?1 x emios?. ?in table 4,?spc564a80 signal properties? /column ?name? updated the following rows: dspi_d_sck /gpio [98] -changed ?-? to cs[2] dspi_d_sin /gpio[99] -changed ?-? to cs[3]. ?in table 12,?thermal characteristics for 324-pin pbga? / column ?value? added conditional text. ?in table 21,?dc electrical specifications? made the following changes: -for the value ?v ol_s ? parameter changed from ?slow/ medium/multi-voltage pad i/o output low voltage? to ?slow/m edium pad i/o output low voltage?. -added a new row for ?i ddstby27 ?. -for row ?i ddstby (operating current 0.95 -1.2v)? added max value ?100? and changed typ value from ?125? to ?35?. -for row ?i ddstby (operating current 2 - 5.5v)? added max value ?110? and changed typ value from ?135? to ?45?. -for symbol ?i ddstby 150 (operating current 0.95 -1.2v)? added max value ?2000?, changed typ value from ?1050? to ?790?,c cell changed from ?t? to ?p? and for symbol ?i ddstby (operating current 2 - 5.5v)? added max value ?2000?, changed typ value from ?1050? to ?760?, c cell changed from ?t? to ?p?. -removed note 9 and note 10 (characterization based capability) from symbol ?v ol_hs ? . ? splitted table 28,?eqadc conversion s pecifications (operating)? into table 29,?eqadc single ended conver sion specifications (operating)? and table 30,?eqadc differential ended co nversion specifications (operating)? . ?in ta b l e 3 0 ,?eqadc differential ended conver sion specifications (operating)? made the following changes: -added the note of diff cmv on all of the diff specs. -min value changed from (vrh-vrl)/2-5% to (vrh+vrl)/2-5 % and max value changed from (vrh-vrl)/2+5 % to (vrh+vrl)/2+5 %for diffcmv. ?in ta b l e 3 1 ,?cutoff frequency for additional sram wait state? made the following changes: -added note ?max frequencies including 2% pll fm?. -max operating frequency changed from ?96? to ?98? and ?150? to ?153?. ?in section 3.13, ?configuring sram wait states , changed text from ?spc564a80 4m microcontroller reference manual ? to ?device reference manual?. table 56. revision history (continued) date revision changes ? ? ? ? ?
document revision history spc564a74l7, spc564a80b4, spc564a80l7 156/157 doc id 15399 rev 9 21-mar-2012 8 (cont.) ?in table 32,?apc, rwsc, wwsc settings vs. frequency of operation , ? - added note for ?max flash operating frequency(mhz). - changed values from 30, 60,120, 150 to 20,61,123, 153 respectively in max flash operating frequency (mhz). ?in ta b l e 3 3 ,a ,?flash program and er ase specifications? dded two parameter ?t psrt ? and ?t esrt ?. ?in table 41,?external bus interface maximum operating frequency? , replacedthe <= symbol in notes with ?? ? added note ?refer to table dspi timing fo r the numbers? in all the figures under section 3.17.8, ?dspi timing . in ta bl e 5 5 , changed lbga208 to mapbga and changed all packages to 123xxxx format. ? added table 17,?spc564a80 external network specification? . ? updated figure 8 . ? changed external network parameter ce min value to ?3*2.35 f+5 f? from ?2*2.35 f+5 f? in table 17,?spc564a80 external network specification? . changed trans. line (differential zo) unit to from w in table 25,?dspi lvds pad specification? . 18-sep-2013 9 ? updated disclaimer. table 56. revision history (continued) date revision changes ? ? ? ? ?
spc564a74b4, spc564a74l7, spc564a80b4, spc564a80l7 doc id 15399 rev 9 157/157 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particul ar purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ? automotive, automotive safe ty or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

▲Up To Search▲

Price & Availability of SPC564A74L7CFAY

	To Download SPC564A74L7CFAY Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .